Fragmentation threatens the roadmap for advanced lithography
As the industry approaches 22 nm, different kinds of fabs may be headed for very different kinds of lithographic tools.
By Ron Wilson, Executive Editor -- EDN, July 17, 2009
Inexorably the day of reckoning in which we must give up 193-nm lithography is drawing nearer. Thanks to immersion optics, double-patterning, and computational-lithography techniques we have pushed that day out beyond the start of the 22-nm node. But such fortune won't go on forever.
At some point only a few years from now, either EUV (extreme ultraviolet) lithography will have to deliver on its protracted promises, or other technologies will have to step in for exposing the critical layers on advanced wafers. Either way, it seems increasingly likely that the lithography roadmap will at that point fragment into a number of incompatible approaches. These approaches will have very different implications for chip design teams. And supporting several branches in the litho roadmap could be a crushing load for an already-stressed materials business.
The wedge issue that creates the fragmentation will be throughput. None of the plausible patterning technologies can today demonstrate production-level throughput, and each has its own challenging path to address the problem.
First there is EUV. Two experimental EUV systems from ASML are running today. The systems have demonstrated their ability to create isolated patterns fine enough for 22 nm, but very serious challenges remain for exposing whole wafers at production volumes. The most worrying is the source of the EUV radiation. There is still question as to whether either of today's source technologies can scale to high-enough intensity to give the short exposures necessary for production throughput.
A related challenge is the search for an optimized resist chemistry. More sensitive resist would mean shorter exposures. But more sensitive resist could also mean increased line-edge roughness and decreased resolution, not to mention greater cost. Resist is still an unsolved problem, although no one seems to be expecting any deal-breaking issues to emerge. It's just going to be a long, costly development.
A recent announcement from IMEC highlighted yet another area of concern: mask technology. The basic form of masks for EUV—for instance, whether or not they will be protected by a pellicle—has not yet been set. And the problem of cleaning the masks is sufficiently interesting that IMEC and a partner have formed a research project to explore it. Chemistry is emerging for the cleaning task. But the necessary cleaning interval is not yet know, nor is it clear how exactly to handle the fragile structures so as not to damage them or allow recontamination between storage, cleaning station, and EUV column.
Every new lithography node has its development challenges, of course. But as Michel Brillouët, deputy director of the Laboratoire d'électronique et de technologie de l'information (Leti) put it, "The thing that concerns me is that the challenges for EUV don't look like development projects. They look like basic science."
If these problems are resolved in time, EUV will be the tool of choice for high-volume wafer manufacturing: commodity memories, microprocessors, graphics chips, and probably some consumer ICs. This is good news for custom-design and layout engineers of these devices, as the potentially excellent resolution of the EUV system would eliminate most of the sub-wavelength complications, such as complex design rules for optical-proximity decorations, from their work.
But the crushing price tag for the equipment and the expected high mask cost will probably put even a successful EUV technology beyond the reach of moderate-volume projects and mid-sized fabs. And that's where an alternative—e-beam direct-write—is starting to look very plausible. "We believe there is a market for direct-write e-beam systems in the lower-volume applications," said Ines Stolberg, manager of strategic marketing at e-beam vendor Vistec.
Direct-write systems activate the resist not by projecting the image of a mask onto the wafer, but by writing directly onto the wafer with a moving electron beam. The advantages of the approach include the enormous theoretical resolution offered by the very short wavelength of electrons and the maturity of the technology. E-beam systems have been making masks for years, and are used to expose wafers in some applications today. The primary disadvantage of the technology is speed: exposing an entire 300-mm wafer with a single scanning beam would take weeks.
Two equipment vendors are taking two quite different approaches to the throughput question. Vistec is using a shaped-beam system. Instead of focusing the electron beam to a circular spot on the wafer and then scanning, Vistec first deflects the beam through a stencil that contains a character set of pre-defined shapes. These shapes might include various rectangles, squares, and elbows, for example. So instead of raster-scanning across the wafer, requiring many hundreds of scan segments to make up a feature, the shaped-beam system forms the features by projecting one, or a few, patterns onto the wafer. The time savings is substantial.
It is substantial enough that, if you use a cell library and memory compiler designed to employ a small set of characters, and put those characters on the stencil, you can expose an entire wafer fast enough for prototype, or even early-production, processing. That is exactly what the eBeam Initiative is promoting, and what is in fact being done at Fujitsu subsidiary eShuttle. But it is not a substantial enough speed-up for full production work. To that end, Vistec is designing a multi-beam system, according to Stolberg. The system will deflect each beam individually through the stencil or stencils, and then collimate them into a single set of electron-optics above the wafer. Vistec is silent for now on details of throughput, or what design limitations might be required to permit the multiple beams to operate together.
Meanwhile Mapper Lithography is working on a scanning-beam approach that achieves high throughput not by projecting characters, but by scanning with a massive number of beams. According to Brillouët, the current Mapper prototype system uses 110 beams, and the system now under development will use 13,000 simultaneous beams. Brillouët expects a single 13,000-beam Mapper station to achieve ten wafers/hour. The stations will be grouped into ten-station clusters, creating a tool with 100 wafer/hour throughput, just plausible for a modest production fab.
Mapper is working with Leti, and has done concept demonstrations at 45 nm with STMicroelectronics. The company has also signed a widely reported contract with TSMC.
That last bit indicates the nature of the coming fragmentation. While a huge memory fab, in which volume is everything, can benefit from EUV technology, the promise is much less appealing to a foundry running many different small wafer lots. Venting the vacuum chamber, handling the fragile EUV masks, recleaning, and pumping the chamber down again to change masks is not an issue for continuous runs of DRAMs or long runs of handset chips, but it is not feasible for the rich mix of designs in a foundry. A foundry like TSMC might only be able to use an EUV system for two or three customers of its largest customers.
Hence some experts are beginning to think of EUV and e-beam not as alternatives, but as complements. For foundries in particular this sounds appealing. Without an alternative to EUV, all but the highest-volume designs could find themselves stuck at 30 or 22 nm with no migration path.
But for the industry, warned Rick Hill, chairman and CEO of Novellus, the two-track scenario is a nightmare. "There are huge costs involved in developing resist technology for either EUV or direct-write," Hill said. "Can the industry really afford to do both right now?"
Further, Hill pointed out that even if we do somehow succeed in making both paths production-ready, there is still a big gap between the smallest project that can afford EUV lithography and the largest project that will be practical for the multi-beam e-beam systems. "Those projects that fall in the gap will be stuck at whatever geometry 193-nm lithography can support," Hill said.
Thus the best-case scenario might be three branches: EUV for the largest projects, direct-write for small-to-medium projects, and 193-nm immersion with all the available tricks for the projects in-between. Each of these tracks would likely have its own libraries, design-rule decks, physical design flows, data-preparation flows, and yield issues, imposing three parallel tracks on the EDA industry, as well. As Hill warns, it is not at all clear that the resist business and those companies that must support it with developing, cleaning, and removal technology; the EDA business; or the big foundries that will have a mix of high- moderate- and low-volume jobs can afford all three.
The worst-case scenario is that at least one of the new technologies can't be made production-ready in time. At that point, according to IMEC Executive Vice President of Business Development Ludo Deferm, the only alternative may be to delay the next process node until something can be made to work. Given the industry's previous experience with 157-nm lithography, that delay could be indefinite.
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Well if you do the units conversion, 20 mJ/cm^2 becomes 1250 eV/nm^2, which would break ~300 bonds per square nanometer. But this is a random event, so originates the line edge roughness. In a sample of a billion, the number of bonds broken can fluctuate more than 30% easily.
statistician - 2009-30-7 08:04:00 PDT -
Ron’s article on the fragmentation of the lithography roadmap is certainly timely, and, in many ways, consistent with what we have been saying: market and customers needs are diverging at such a rapid rate, it is growing less and less likely that a single lithography technology will meet all those needs. Markets can be segmented in numerous ways: Ron opted for volume for his framework. We believe another meaningful segmentation is around cost of ownership and resolution. One need only look at (1) the ITRS to see the resolution divergence between memory, particularly NAND flash, and MPU/logic, and (2) the ASP and profit margin per unit area of MPU vs. NAND flash wafers to reveal two radically different markets. Furthermore, NAND has been, and promises to remain, one of the most elastic of all semiconductor markets. By achieving lower costs and higher densities, NAND has helped open numerous new markets including MP3 players, digital cameras, and others. And the big kahuna, the solid state drive market, remains on the horizon. Of all the lithography candidates being investigated for sub-32-nm patterning, the one that has demonstrated the most compelling combination of resolution and cost-of-ownership advantages for NVM manufacturers is nanoimprint lithography. With imprint, feature resolution is limited only by what can be etched on a mask with an e-beam writer. In fact, imprint has demonstrated feature printability down to 12nm. Imprint also uses traditional optical masks available from traditional mask makers, as well as commercially available I-line source and resist technologies. Finally, with imprint the cost of the tool is independent of resolution – something that has never happened before in the semiconductor industry. Indeed, NVM producers are beginning to perceive imprint as significantly less risky than EUV, which continues to have “basic science” problems as Ron points out in his article.
Ken Rygler - 2009-22-7 14:17:00 PDT -
Shot noise, LER will put an end to the usual exposure by radiation as the means for feature definition. Cannot catch up on throughput.
no more lithography - 2009-20-7 18:53:00 PDT -
EUV photoelectric charging could lead to ESD. A lot of basic stuff still ignored so far.
ESD - 2009-18-7 08:50:00 PDT -
With the emphasis on green technology, it should be a concern that more energy will be consumed for lithography for EUV or electron beam. An EUV photon costs 14 times as much energy as 193 nm, while the electron acceleration costs about a thousand times as much if not more. If you use fewer photons for the same resolution, I get more roughness (remember the textbook example of the photo of the woman?). The semiconductor industry has never been a fan of sudden changes. The cost of sudden change exceeds incremental costs, generally.
greener - 2009-17-7 18:55:00 PDT
