Start-up offers dynamically reconfigurable logic technology
By Graham Prophet, Europe Editor -- EDN, August 6, 2009
Start-up Akya is offering IP (intellectual property) to allow IC designers to include reconfigurable logic on their ASSPs (application-specific standard products) or ASICs (application-specific integrated circuits). The company delivers both reconfigurable-logic fabric and IP blocks to execute commonly required functions on that fabric. Colin Dente, the company’s chief executive officer, says that the reconfigurable logic can be a part of a larger chip design or form the basis of a complete IC. Akya calls its technology ART2. The ART2 architecture separates data flow and control logic to simplify design and implementation of reconfigurable structures.
Akya’s technology differs from other concepts that companies have marketed as dynamically reconfigurable. “If I could think of another term to describe what we do, I would use it,” says Dente, explaining that the architecture is not completely general-purpose, but that the company designed it to be just reconfigurable enough to do what is necessary in applications such as audio/video codecs and communications-signal processing. The company claims that the technology is particularly efficient at DSP functions.
Any engineer familiar with HDL (hardware-description-language)-based design can learn how to use the tools, which allow you to design a fabric that targets a specific application. This fabric comprises and draws on an IP library of processing elements. These elements are typically at the level of arithmetic functions rather than being fine-grained, gate-level elements. To this fabric, you add an address sequencer and a programmable interconnect to yield a set of processing resources that match your design. The design tools then assist you in creating an explicit control flow for the design, and you can change that flow after the silicon becomes final. The reconfigurability materializes under the direction of the control flow. With every clock cycle, you can completely reconfigure the datapath: You specify which action each processing element is to carry out on a cycle-by-cycle basis.
Doing the control programming is somewhat similar to writing code for a processor. However, the device you work with is not a VLIW (very-long-instruction-word) processor. It does not write and read data to and from memory, and the minimal use of such transactions is one of the sources of Akya’s claims of very low power usage: “In [silicon] area and power, we are right at the custom-silicon end of the [design] spectrum,” Dente says, adding that portable and battery-powered products are targets for the technology. In part due to the architecture’s processing efficiency, clock speed is unlikely to be a constraint for most telecommunication or audio/video-processing functions.
Thanks to the technology’s reconfigurability, it reduces the risk inherent in IC design, takes half the design time of RTL (register-transfer-level) design, and lets you quickly modify designs without changing the silicon itself. With a reconfigurable block, you might make one mask set that serves for several designs, making a custom IC viable when it otherwise would not be. The company offers a similar argument for the problem of adapting an IC to changing standards.
Akya supports ART2 with a development kit that features one high-level language for data flow and another for control; the company also provides comprehensive training in the ART2 architecture compiler. ART2 is available now; the first commercial chip incorporating the technology is in development and will be on sale in an end product in 2010.
