Lattice launches midrange FPGAs at cellular and access networks
Lattice's ECP3 family begins to look almost application-specific in its details.
By Ron Wilson, Executive Editor -- EDN, February 23, 2009
The mid-range FPGA market—roughly, devices equivalent in size to a small SOC or modest gate array and costing up to about $75 each in quantity—is a difficult place to find a foothold. It is the goldmine of the FPGA market, where the profits are, and powerful families from Altera and Xilinx have the territory well staked out. So smaller players, who have to live with more mature processes and lower development budgets, must find a differentiation not based on pure logic density or—worse—cost. This pressure is gradually making mid-range parts increasingly, if not application-specific, application-directed.
An excellent case in point is the ECP3 family, announced this morning by Lattice Semiconductor. Ranging up to about 150 K look-up tables (LUTs) and selling for about $50 each in 25K quantities for a 92 K LUT device, the family hits right at the heart of the FPGA mid-range.
While nominally a general-purpose FPGA family, the ECP3s are clearly aimed at a fairly narrow set of applications. Lattice director of strategic marketing Shakeel Peera identified several such areas, including enterprise and access networking cards, cellular base stations, and TV broadcast studio networking. While these applications appear in different markets, they have a great deal in common: high-speed serial I/O with modest but not telecom-grade SerDes, pre-emphasis, and equalization needs; significant signal-processing loads on some very specific algorithms; significant memory requirements, including both a large amount of fast internal buffering and access to high-speed external DRAM; and modest random logic appetites.
By no coincidence whatsoever that list could be the feature bullet-points for the ECP3 family. Lattice bills it as the lowest-cost, lowest-power entry in the market for mid-range FPGAs with SerDes on-chip. Substantiating those claims would be nearly impossible, given the mysteries of FPGA contract pricing and the even greater mysteries of FPGA power consumption, but Lattice's intent is clear.
The company is using Fujitsu's conservative 65-nm process at 1.2V core voltage for the devices, and employs a similarly conservative SRAM-based 4-LUT-plus-flipflop cell architecture. Peera said that the architects' emphasis in the programmable fabric was to manage static and dynamic power, not to go for blinding speed. Hence the chip designers chose the high-threshold transistors from Fujitsu's multi-Vt process for the logic fabric. Consequently, Lattice is quoting a respectable but not eye-threatening 350 MHz for block-level clock frequencies. Peera says that represents performance on carefully-designed circuits with only a few gate delays between registers.
The real interest in the ECP3 family lies in the embedded functions that are keys to those target applications: the SerDes, memory architecture, and DSP blocks. This is where the Lattice engineers lavished their efforts and their low-Vt transistors.
The SerDes blocks, Peera said, are a careful balance of performance enough for the selected applications, but low cost and power. There are between four and 16 SerDes channels available per chip in the family. Maximum frequency is 3.2 Gbits/s, sufficient for applications like SONET/SDH, most backplane interconnects, or PCI Express 1.1, but not for PCI Express gen-2 at 5 Gbits/s.
The internal design of the blocks is interesting. The SerDes channels are organized to share one clock source for four channels, with individual clock multiplier/dividers for each channel. There is hardware support for the simple 8b/10b protocols Lattice had in mind, and up to 12 dB equalization. So while the blocks are not intended for complex signaling, they are robust for 3 Gbits/s over up to 40 inches of FR4. The benefits of these choices include a small footprint and 90 mW/channel operation.
An interesting side note here, and an example of the thought that has gone into the ECP3s for specific applications, involves PCI Express. Lattice has chosen to implement the 1.1 interface with a deterministic controller design, so that MIMO base stations can maintain the phase relationships between channels.
Another example of Lattice's concentration on power and cost in this area is in the clock inputs to the chip. Peera explained that the ECP3s are designed to use CMOS oscillators rather than LVDS oscillators. Analog circuitry on the FPGAs does clock multiplication or division and conversion to LVDS levels for on-chip distribution, with maximum jitter around 2.5 ps.
The designers took two major steps in the memory area. The first was to lavish chip area on SRAM: a total of 7 Mbits on the largest parts. In addition, the chips provide the I/O and embedded controller to handle a DDR3 interface at 400 MHz or support RLDRAM-II. The DDR interface requires about 2K LUTs of the logic fabric in addition to the hard macro.
Finally, one of the quiet changes in the mid-range FPGAs, including the ECP3 family, is the growing sophistication of the embedded DSP blocks. Originally, the idea of embedded signal processing macros was simply to provide a scattering of 18-by-18 multiply-accumulators in hard logic around the programmable fabric. MACs are notoriously hard to implement—and slow—in programmable logic, so just tossing a bunch in helped considerably with fast signal-processing issues.
But today it is clear that even in the mid-range market FPGA architects are testing their DSP macros against specific customer algorithms. "Algorithms like power-factor reduction in OFDM base stations, or pre-distortion in wireline communications require DSP pipelines with not just MACs, but adder trees, as well," observed Lattice VP Sean Riley. "So we have included a 54-bit ALU hard macro. That way customers don't have to implement it in the fabric."
Clearly Lattice has made a strong effort to make up the process-generation gap between themselves and the big two of the FPGA world by clever application-directed engineering. Whether that will be enough remains to be seen. Many members of the ECP3 family—except the largest device—are available immediately. But they won't have a long window before they are facing, for example, Altera's 40-nm Arria II. That family overlaps the ECP3 family from the middle of its range to the high end, offering up to 256 K LUTs and 11.8 Mbits of RAM in a 40-nm TSMC process running at 0.9 V. And it has up to 16 channels of slightly faster SerDes, at 3.75 Gbits/s, although that speed difference won't be significant for most applications. What might be more significant is that the Altera parts provide less equalization range, at 7 dB maximum. The Arria SerDes are not intended for messy backplane applications.
So it may come down to a classic battle of process-derived technical advantage versus architecture- and circuit-derived application advantage. It's not going to be an easy battle for Lattice. But it appears that the smaller company has mounted a strong enough challenge that it's not going to be easy for Altera or Xilinx, either.
Figure 1: The ECP3 DSP modules are designed for cascading to satisfy wireless signal processing requirements.
