Power-rail filtering improves PLL performance
Use careful decoupling to reduce phase-lock-loop jitter and noise.
By Rick Rabinovich, Alcatel-Lucent -- EDN, March 19, 2009
The engineer has to design in power-rail filtering to meet the manufacturer’s specifications for output clock jitter in phase-lock loops (PLLs) and crystal oscillators. There are two types of power sources, voltage and current (
). A voltage source keeps its output voltage level constant and presents a low-impedance output. A current source keeps its output current constant with a high-impedance output. A decoupling component is a two-pin device that provides a low-impedance path between the power rail and ground. This gives a local storage of energy to service sudden current demands by the target load. A filter is a three-pin device that alters the transmission of a signal by enhancing or suppressing some of its frequency components (
).
The output clock quality of a PLL circuit is highly sensitive to power supply noise. IC manufacturers define PLL power filtering requirements by specifying the maximum voltage noise ripple at the power pins, say, 10mV, as well as the filter attenuation required of such noise as a function of the frequency, for example, -3dB at 50 kHz. To decrease power supply noise, you need to increase the power-rail impedance between the voltage source and the PLL circuit load by placing a current source between them (
). The filter should also provide a dedicated voltage source to the PLL load.
In a typical PLL circuit configuration (
), V1 represents an ideal voltage source that generates a dc voltage with some inherent ac ripple. R1 represents the source series resistance as well as the power-rail circuit board trace resistance. The ferrite bead U1, the current source, and the capacitor C1, the voltage source, form a low-pass filter between the voltage rail and the load. C1 delivers power for low frequency load surges. The decoupling capacitors C2, C3, and C4, in parallel with the load, are also voltage sources that deliver high-frequency current for load surges. The impedance of a ceramic capacitor decreases with frequency until the capacitor reaches its resonance frequency (
). Above the resonance frequency, the capacitor behaves like an inductor. The resonance frequency is a function of its value and package (
).
The load is represented by current source I1, which generates current pulses dependent on the PLL operation. Place a decoupling capacitor C5 on the line side of ferrite bead U1 to absorb any high-frequency components generated by the power source. In this example, the power rail is 3.3V DC or lower. The bulk capacitor C1 is responsible for holding the IC power pin voltage within a predefined voltage tolerance from the nominal value. Select a bulk ceramic capacitor based on its value, low equivalent series resistor (ESR), and package size. A good compromise is a 22- to 47-μF ceramic capacitor, rated at 6.3V, in an 0805 package with a typical ESR of 3 mΩ. The equivalent series inductance (ESL) of the 0805 package is about 600 pH.
Select capacitors C2-C5 to keep low impedance between the IC power pins and ground at frequencies above 10 MHz. These capacitors should be ceramic XR5 type, with a value of 0.1uF, in an 0402 package size. They are rated at 10V with a tolerance of 10%. Their impedance is 31 mΩ at their resonance frequency of 26 MHz. The package-dependent ESL is 400 pH. You could select C3 and C4 with values of 0.01 and 0.001 μF, although an unwanted resonance frequency can occur when mixing high-frequency capacitors of different values. The voltage ratings for ceramic capacitors should be derated by at least 20%. For example, if the voltage rail to be decoupled is 3.3V, the capacitor voltage ratings should be 5V or higher. The filter’s low-frequency response is dominated by C1.
To minimize the impedance between the IC power pins and ground you should use a minimum of three high-frequency capacitors even if there are fewer than three IC power pins. If the load consists of more power pins, use as many capacitors as there are pins. The decoupling capacitors chosen here are of the same value to avoid peaking between the resonance frequencies. When frequencies higher than 20 MHz need to be filtered out, smaller capacitor values such as 0.01 and 0.001 μF may be required. Mixing capacitors of different values may be acceptable as long as the unwanted resonance frequency peak does not exceed the maximum voltage rail impedance required. Place C2-C4 as close as possible to each power pin.
The ferrite bead should be a low-resistance power-line type to provide adequate current rating. You should pick a bead with impedance in the range of 300 to 400Ω for current loads of 500 mA or less (or lower impedance for higher load currents) at 100 MHz. Try to use a ferrite bead with a 0603 package size to reduce parasitics, and reduce the length of PCB traces to the IC. You should place U1 and C1 close to each other and near the PLL load. A 300Ω ferrite bead would have a lower dc voltage drop, but the noise dampening factor would be lower as well. A 390Ω bead will have a higher dampening factor but also a higher dc voltage drop.
Ferrite bead families have a broad range of frequency operation. For example, TDK offers the R class for crystal oscillator frequencies up to 70 MHz (
, 
). You should use the S class for crystal oscillator frequencies above 70 MHz and ICs in general.
Power-line filter simulations
You can use a program such as Linear Technology’s LTSpice to simulate the power-line filter performance for three different cases. If you remove the bulk capacitor C1 (
), the voltage at the load oscillates severely (
). The ferrite bead inductor creates an LC tank with the parallel capacitors C2-C4. The period of the oscillation is 3.77 μs and the oscillation decays by 90% in 72 μs. Adding bulk capacitor C1 and using a 390Ω ferrite bead suitable for lower-frequency ICs (
) can reduce the oscillations to manageable levels (
). The oscillation frequency is approximately 14 kHz and the amplitude is reduced to less than 10% in 104 μs. The 3-dB filter attenuation occurs at 21 kHz. The damping ratio is 0.24.
For higher frequency ICs you can use the 330Ω ferrite bead of along with a bulk capacitor (
). This also provides for a manageable power-line oscillation (
). The oscillation frequency is 20.8 kHz and the amplitude is attenuated to less than 10% in 72 μs. The 3-dB attenuation occurs at 32 kHz. The damping ratio is 0.24.
Conclusion
You need to pay close attention to the component selection of power-line filters. The ferrite bead impedance must be large enough to produce sufficient isolation between the voltage rail and the load. The dc resistance must be small enough to avoid excessive voltage drop. Make sure the resonance frequency oscillations created between the ferrite bead inductance and the bulk capacitance are acceptable for your design. Mixing high-frequency capacitor values can cause unwanted resonance effects. However, mixing capacitors may be acceptable as long as the impedance at the resonance frequency between different capacitors values does not exceed the maximum allowable voltage-rail impedance. In general, follow the IC or crystal oscillator manufacturer recommendation, but always challenge the adequacy of a generic solution.
| Author Information |
 Rick Rabinovich is a senior principal hardware engineer at Alcatel-Lucent. He has previously authored several technical articles and holds a US patent in communications. He was also the main speaker in a Southeast Asian Hewlett-Packard Embedded Processor design tour. Additionally, Rick is a voter member of the IEEE802.3 Ethernet and has held positions at Spirent Communications, Telematics, Ascom-Timeplex, Singer Librascope, and Northrop.
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Well, it turned out that the sneak path was not through the power pin, but through the VCXO''s own output. Same effect of unwanted oscillator pulling, different coupling mechanism.
The VXCO output drives a buffer (hex 74AC14 Schmitt) in the same package as the buffers that are driven by the FPGA phase detector which in turn drive the VCXO control voltage. The common buffer package is the culprit, the faster edge transitions of the new FPGA phase detector are coupling through the common buffer package (ground bounce from bond wire inductance maybe?) into the VCXO output. This coherent feedback is pulling the oscillator frequency causing it to chase it''s own tail.
The easy solution is to remove the VCXO output buffer, not really needed in this application. With the unwanted coupling eliminated the circuit now works as intended even with a thick coating of frost on the FPGA.
Mixing analog oscillators with digital can result in some very strange effects. When your phase locked loop won''t, check for sneak digital noise couplings.
Thanks again Rick for this timely article.
Glen Chenier - 2009-28-4 00:19:00 PDT -
Continuation of previous truncated post...
...This article has just reminded me of the power noise problem; it is possible that the newer and faster FPGA may be increasing the power supply noise level with shoot-through current spikes stronger than that of the older slower FPGA. So first thing Monday morning I am going to pull the VCXO and insert a choke/capacitor into it's Vdd supply as a rough test.
Mr. Rabinovich, thank you for this article.
Glen Chenier - 2009-18-4 20:21:00 PDT -
Why is this article not in the 19Mar09 print or online editions of EDN?
Mr. Rabinovich describes a hardware ''gotcha'' that no simulator can predict. The oscillator of a PLL can be very sensitive to noise riding on the power rail, especially if that noise is coherent, ie digital noise caused by the oscillator itself.
I''ve run into this very problem prior to now. A master PLL that sources timing to a slave unit at the far end of a communications cable will see a delayed version of itself in the digital power supply noise resulting from the returned signal of the slave unit. The delay results from the cable length, and the supply noise reflects the oscillator phase as it was hundreds of cycles in the past. When the oscillator gets pulled by it''s own delayed digital noise it tries to lock to that noise and fights the local loop control. The result is a PLL that jitters terribly as it tries to chase it''s own tail.
I am currently fighting with a PLL that goes insane when the FPGA containing the phase detector is cooled to about +10C. We are attempting to migrate to a new FPGA (faster silicon, same functional load) to maintain production on an existing circuit board, the original FPGA is no longer manufactured. All our tests so far indicate that the FPGA itself is functioning properly. This article has just reminded me of the power noise problem
Glen Chenier - 2009-18-4 17:27:00 PDT
