Virage Logic introduces multi-time programmable 65-nm non-volatile memory
-- EDN, May 20, 2009
Virage Logic Corp has announced it has qualified its AEON nonvolatile memory (NVM) product on TSMC’s 65-nm Low Power (LP) process. AEON enables IC manufacturers to embed NVM at advanced logic processes—something that was previously limited to the use of one-time-programmable fuse technology—and design a multi-programmable product. Eliminating external EEPROM from system designs allows companies to reduce power, area, and cost, and it increases security. AEON also enables product differentiation by enabling features such as in-field customization, calibration, encryption keys, and non-volatile counters.
“AEON brings true multi-time NVM programmability to market segments where advanced-process adoption is crucial, such as security and wireless,” said Dr. Yankin Tanurhan, vice president and general manager for NVM Solutions at Virage Logic. “AEON can replace one-time-programmable solutions with a fully electrically testable NVM block. And because we’ve built reliability into the architecture and fully qualified it on TSMC’s 65-nm LP process, AEON provides a low-risk, highly profitable investment.”
The design of Virage Logic’s AEON NVM is based on a standard logic CMOS process with no additional masks or processes required.
AEON supports 100,000 write-erase cycles and bit counts from eight bits to 8k bits. The AEON product line enables 100% electrical testing at wafer sort and eliminates costly field programming failures associated with one-time programmable approaches. Optimized to enable considerable manufacturing and operational flexibility, final calibration can be performed at wafer test, at post-packaging, or in the field. In addition, identical ICs can be calibrated and configured to implement different features at final test immediately prior to shipping.
