EDN's 19th Annual Innovation Awards Finalists
-- EDN, February 2, 2009
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&& PREVIOUS FINALIST | MAIN | NEXT FINALIST >> Category: EDA: Design Analysis Finalist: PowerArtist RTL tool (Sequence Design) Aimed at the mainstream RTL designer, PowerArtist features an entirely new visualization environment that makes it very easy for the designer to identify where power is being consumed, and how it can be reduced. The tool takes in RTL code and finds opportunities for power reduction. Depending on the optimization it's running, it can automatically rewrite power-optimized RTL, output synthesis constraints, or guide the user through a manual RTL rewrite.These features result in the industry’s fastest automated RTL power reduction – 10 to 50 percent or more depending on the design – in just minutes on a million-plus gate block. Sequence’s long and innovative history in EDA RTL power reduction led it to focus PowerArtist’s on three key areas: Clock, Memory, and Datapath at RTL where designers have maximum opportunities for power reduction. The power savings are over and above those achieved during synthesis. Next-generation engines examine the RTL code, prioritize power reductions, and either maximize power savings automatically or guide the user through manual edits within a powerful graphical environment. A typical concern is “what happens to my RTL?” PowerArtist eliminates this issue by only making very precise, surgical changes to the original code. The automatic rewriting preserves the original RTL formatting without changing the functionality or the timing of the RTL. For example, PowerArtist does not insert clock gating cells, but makes changes so that synthesis will be more efficient at inserting clock gating. PowerArtist integrates with all standard design flows, including synthesis and formal verification. It allows users to automate proprietary power reductions using the Si2 OpenAccess database with its open API. |
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Aimed at the mainstream RTL designer, PowerArtist features an entirely new visualization environment that makes it very easy for the designer to identify where power is being consumed, and how it can be reduced. The tool takes in RTL code and finds opportunities for power reduction. Depending on the optimization it's running, it can automatically rewrite power-optimized RTL, output synthesis constraints, or guide the user through a manual RTL rewrite.






