EDN's 19th Annual Innovation Awards Finalists
-- EDN, February 2, 2009
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MAIN | NEXT FINALIST >> Category: Innovator of the Year Finalist: Stratix IV 40-nm FPGA design team (Altera) ![]() Approaching the design and development of Stratix IV, Altera’s 40-nm design team's goal was to optimize time to market, performance, manufacturability, and cost. With time-to-market pressures and complex design issues, Altera was challenged to close all gaps under a schedule that was much shorter than the regular development cycle. The team formed 12 joint development teams with TSMC to address issues such as power/performance balance, modeling, test-chip planning, DP-SRAM (dual-port SRAM), poly fuse, DFM (design for manufacturability), standard cells, RF/analog, ESD (electrostatic discharge), and ELK (extreme low-k). The development of these “tiger” teams and their close collaboration helped to shave months off the manufacturing and IC-design process. Another core area the 40-nm design team addressed was power management. The team used five innovative methods to reduce leakage current, including increased transistor Vt via doping, increased transistor channel length, the application of thicker gate oxide, increased transistor Vt via Programmable Power Technology, and decreased Vcc. As a result, it was able to deliver 50% lower power and 35% higher performance than competing FPGA devices. The team also built upon Altera's proven transceiver technology to increase the transceiver's performance to 8.5 Gbps, providing even better signal integrity and broadening its range of protocol support, including four hardened PCIe Gen2 cores. One of the most valuable strategies the 40-nm design team implemented was the use of test chips. The use of test chips provided valuable insight into the impact of random and systematic variations and aided in the development of design strategies to reduce or eliminate them. As a result, the team was able to accelerate its 40-nm development methodology while providing the company with the industry's fastest time to advanced processes. |
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