EDN's 19th Annual Innovation Awards Finalists
-- EDN, February 2, 2009
|
&& PREVIOUS FINALIST | MAIN | NEXT FINALIST >> Category: EDA: Design Analysis Finalist: Incisive Palladium DPA (dynamic-power analysis) (Cadence Design Systems)  Cadence Incisive Palladium Dynamic Power Analysis (DPA) represents a methodology shift for power budgeting of electronic devices with system-level implications. The traditional approach is gate-level simulation and/or the use of spreadsheets for power estimation. Using the high-performance Palladium III engine, DPA improves performance and enables design teams to run long system-level tests, empowering SoC teams to correlate performance-sensitive functions’ power consumption with an acceptable user-level experience (QoS).DPA helps engineers quickly identify peak and average power of SoCs with “deep” software cycles (real-world stimuli) at MHz throughput for RTL and gates. Leveraging Palladium III’s built-in memory and RTL Compiler’s power estimation engine, Cadence provides the first high-performance, cycle-accurate integrated solution delivering full-system power analysis of hardware/software designs. Power profiling includes a weighted toggle histogram for all instances, full-chip including design signals. Designers can use the GUI to filter information to pinpoint power-hog blocks. DPA uniquely offers both a telescopic (coarse-grained toggle histogram “over a long run”) and microscopic view (“area of interest” to do fine-grained analysis). With the successive-refinement approach, system designers can now make better decisions of selecting IPs, an “adequate” package, and cooling requirements. Designers can react quickly to changes in specification or environment. By testing against various operational scenarios and “what-if” analysis to make architecture trade-offs, architects and designers can make better decisions to save power. |
|
Talkback
