ST, Soitec partner to develop next-gen CMOS image sensors
Soitec licenses its Smart Stacking process to STMicroelectronics for producing 300-mm wafer-level backside-illuminated image sensors.
By Gail Flower, Contributing Editor -- EDN, May 14, 2009
STMicrolectronics and Soitec announced an exclusive joint cooperation to develop 300-mm wafer-level BSI (backside-illumination) technology for the next-generation of image sensors in consumer electronics.
Soitec released its Smart Stacking bonding technology last month and has agreed to license it to ST for manufacturing BSI sensors in 300-mm wafers. Smart Stacking is a low-temperature industrial process for circuit stacking developed by Soitec’s Tracit business unit -- a spin-off of the CEA-Leti microelectronics research organization, which Soitec acquired -- for wafer-level stacking onto a range of starting materials to improve yields in the production of high-end image sensors in 3D formats. Smart Stacking involves molecular bonding and mechanical/chemical thinning.
ST will use the process to develop a new generation of image sensors based on its advanced derivative-CMOS process technology at 65 nm and beyond at its 300-mm facility in Crolles, France.
Consumer demands for high-quality digital cameras embedded in mobile devices continues to increase. A new generation of back-illuminated CMOS image sensors moves the electronics to the bottom of the stack for light to enter the device directly, resulting in clear pictures or video even under low light conditions. ST has demonstrated the manufacture of 3-megapixel CMOS image sensors with small pitches in a BSI design with a high QE (quantum efficiency) of >60%, which is 15% better than with front side illumination, the company said. (QE indicates the percent of photons converted into electrons.) The BSI design starts with an SOI (silicon-on-insulator) wafer.
“Backside-illumination technology is a key ingredient in the small-pixel, high-image-quality race for the development of leading-edge image sensors,” said Eric Aussedat, group VP and general manager of ST's imaging division, in a statement. “Partnering with Soitec will help quickly deploy the Smart Stacking technology in to ST’s camera products. This agreement will accelerate the development of advanced and superior cost-competitive image-sensor processes, and further confirms the Grenoble region as a world-class center of expertise for advanced CMOS imaging technologies.”
André-Jacques Auberton-Hervé, president of Soitec, said that the agreement is a major step toward new areas like 3D integration markets. “It is demonstrating that innovation is on track to deliver future growth even in a downturn," he said in the statement.
The demand for wafer-level transfer processing is forecasted to reach significant volume production by 2010/2011, according to market research company Yole Development. “By 2012, when the market for 3D integration of heterogeneous components such as memories logic, power ICs, and analog takes off, Soitec’s circuit stacking technology will enable further device design simplification and manufacturing with hybrid function capability and technology integration,” said Eric Mounier, PhD, co-founder of Yole, in a statement.
