IP: final straw that broke the camel's back, or opening Pandora's box?
GUEST OPINION: The future of intellectual property (IP) can be brighter with some work and support by all.
By Bill Martin, Mentor Graphics -- EDN, March 11, 2009
Many conferences, panels, and articles have been written regarding intellectual property (IP) over the past five years expressing both positive and negative but accurate opinions. Many probably wonder if purchased IP is worth the trouble. Can business and technical issues with IP be fixed? Some might think that it is the "final straw" and they will never use pre-designed IP again. Others may think IP might have come out of "Pandora's box."
The camel's back and Pandora's box folklore
The "final straw that broke the camel's back" was described as: small and seemingly insignificant addition to a burden that renders it too much to bear or a small thing which causes failure, inability, or unwillingness to endure more of something.
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Pandora's box: Pandora had been given a large jar and instruction by Zeus to keep it closed, but she had also been given the gift of curiosity, and ultimately opened it. When she opened it, all of the evils, ills, diseases, and burdensome labor that mankind had not known previously escaped from the jar. But it is said that at the very bottom of her box lay hope.
At the beginning
Prior to 1980, most electronic design work was either custom IC development performed by a small niche group of semiconductor engineers using a set of very special skills or system-level design using off-the-shelf IC components on a PCB board. The latter group was much larger than the semiconductor engineers. Before more engineers could perform silicon design engineering, a few key barriers needed to be removed.
Our "pre-conditioning": college bread-boarding labs
Many college EE lab work revolves around bread-boarding circuits using various integrated circuits (ICs). These ICs can be complex (i.e., processor, FPGA, etc.) or simple 74xx TTL logic or even discrete components. We were induced to thinking that off-the-shelf components worked as expected without requiring additional development. Most errors found were due to wiring errors by the student. On rare occasions, a nonfunctional IC was identified. For students, this was one of the toughest areas to investigate since testing an IC in a university lab was difficult; many labs did not have the same equipment or programs used to test the IC. Even after an engineer graduated (and became part of the workforce) he/she might "play" at his/her home with packaged units. It is much easier for a hobbyist engineer to purchase ICs and use bread-boards to construct his/her design rather than to create a silicon chip. Electronic Design published an article on February 18, 2009, by Louis E. Frenzel titled Whatever Happened to Heathkit? We continue to re-enforce the off-the-shelf IC thought process.
Infrastructure evolution: languages, tools, and methodology
Without providing higher-level languages to create designs, IC engineers were relegated to placing components into a schematic for their design. Many IC designs prior to 1980 were developed and simulated with SPICE decks. SPICE models are very intricate, requiring many parameters to accurately predict actual silicon performance. In those days, most of the physical layouts were a hand-crafted, time-consuming, and error-prone undertaking.
Four key initiatives converged to dramatically change the ASIC environment. Without all of them, the "basic ASIC" might never have been achieved.
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Many companies had an economic incentive for their system engineers to develop their own silicon chips.
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High-level languages (Verilog/VHDL) were created, which allowed more system engineers to implement their ideas in ASIC designs without dealing with the associated device physics.
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EDA tools enabled these designs to be synthesized into gates, whereby they could then be simulated and routed at the gate level, rather than at the tedious transistor level. Most gates were primitive, such as NAND, NOR, etc. A few higher-level functions such as Memories and 82XX macros were also becoming available, but these functions were only available and "characterized" in the ASIC provider's silicon. Higher levels of abstraction allowed a larger number of system designers to quickly design silicon chips without understanding the detailed physics' of the underlying silicon transistor. Understanding SPICE models and their parameters were no longer required for the "masses," and the number of ASIC designers grew many-fold.
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In these early "ASIC days," while few designs worked the first time, at least the full mask set was relatively cheap. Companies that provided ASIC silicon, tools, and services had profit incentives to quickly evolve their methodologies to increase first-time success. At the same time, ASIC vendors were required to focus on many designs and manufacturing aspects to ensure their customers' success as well as their own. This included ensuring that any IP (base libraries, "mega-cell" IP blocks, Memories, etc.) was fully verified and validated on their tools and silicon processes. ASIC vendors had "self-interest" for high-quality IP and lower-level building blocks, because they reaped the benefits through their silicon margins. Often, IP was bundled into the overall unit pricing (oops: a hidden royalty!). If customers wanted to move their designs from one ASIC vendor to another, they were told that they were locked-in with their specific vendor or were required to pay high transfer fees and/or endure significant migration efforts. After a short period of time, many ASIC customers/purchasers wanted freedom of choice on where to buy production units.
Foundries: silicon freedom of choice!
One of the final pieces in the evolution of ASIC industry disaggregation was to establish large silicon foundries. These foundries focused on creating high-volume fabrication sites that could support many customers and, most importantly, very efficiently and with competitive pricing. The demand grew rapidly, as various technical challenges had been overcome. Now was the time to harness unlimited silicon supply and increasing densities. But, when IP became disassociated with both the design flow and silicon process, IP quality suffered. Most of the existing IP was developed and silicon-validated by ASIC vendors, coupled with their tools and processes. This IP would not easily migrate to other vendors' processes. The number of IP variations quickly grew based on some of the following factors:
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The multitude of foundries (TSMC, Chartered, UMC, IBM, SMIC, etc.)
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Each of their processes (130nm, 90nm, 65nm, 45nm, Bulk vs. SOI, etc.)
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Process options (general purpose, low power, and high performance)
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Various supply and I/O voltages (5, 3.3, 2.5, 1.8, 1.4, 1.2, and 1)
These variations overwhelm most IP providers. As a consequence, IP providers must carefully choose which variations of tools/flow and foundries to support in order to yield an acceptable return on their investment (ROI).
Unfortunately, as the foundry industry moves down to smaller processing nodes, the "IP quality gap" continues to increase. Few ASIC design teams can keep pace with the full integration potential offered by a new node as they wait for IP vendors and tool vendors to catch up to the foundries' latest offers. One way to help narrow the gap is by using pre-engineered IP blocks.
Is IP a piece of straw that has broken the camel's back, or is it a curse, released from Pandora's box?
Neither one! When it comes to IP, the industry has no option. IP is a vital aspect to: addressing the design gap; shortening time-to-market; succeeding with fewer development resources; dealing with growing system complexity; and increasing development risks. IP is not a piece of straw that has broken our backs. It is a vital component that we must improve and learn how to harness just as we harnessed the power of basic ASIC.
As with Pandora's box, there lies hope in the box. Evidence of this hope is already apparent:
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As quickly as the foundries created multiple process variations, they quickly realized that differentiation is expensive. Fabrication alliance and "industry-standard processes" continue to gain acceptance to help share the development and production costs, causing many foundries to produce the same process recipe with the same equipment. This offers built-in second sourcing options for their customers, thereby reducing their supply risks. For the IP suppliers, this reduces the process variations required to validate their IP. With fewer variations, thoroughly validated, higher-quality IP can be delivered. This trend will continue and thus reduce the complexity for customers and suppliers.
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Various quality metrics, tools, and industry certification processes have been released. Although the current generation is not complete, they will evolve into an effective means to ensure delivered IP that works as expected. Customers and suppliers need to use these tools and methods as well as enhance their usefulness by providing feedback on ways to improve them.
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Development and acceptance of higher-level subsystems has occurred. Subsystems combine multiple subcomponents into fully tested larger IP blocks, loosely combining digital, analog, and embedded software IP. Achievable densities in current silicon evolution in subsystems will be realized by "hard IP" in which both the digital and analog components are routed as a unit supporting configuration via programmability. Programmability can be supported by software registers or be hardwired. The number of gates consumed by this technique will have minimal impact on the die's size and therefore cost.
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In addition, given the GHz speeds the industry is approaching for these subsystems, it makes sense for the IP developer to create pre-routed blocks that achieve gigahertz performance requirements, eliminating difficult place and route (P&R) integration challenges. Besides helping their customers, this also reduces the IP suppliers' support burden for these blocks. This is enabled through the fabrication alliances mentioned previously. Without these alliances, too many variations would be required for each subsystem.
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Realize that royalties have always been present in a price model even if not expressly stated. They can be easily hidden in overall pricing (unit or services pricing, for example). However, the old adage "you never get something for free" is true. Just because someone thinks they got a great price does not mean they got a good deal. The long-term "cost of ownership" implies that a common understanding royalties and fees may be the wiser choice for both the vendor and the customer.
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Understand that silicon IP is different than packaged ICs. Silicon IP allows too many variables to be "tinkered" with compared to package ICs. This IP flexibility can be costly. When the industry moves toward fully routed subsystems, this might move silicon IP closer to our IC experiences. If a subsystem is fully routed and silicon validated, it does not require much more expense to offer packaged "golden units" for the customer to evaluate.
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With silicon IP success, we can achieve wide-spread adoption of ESL. Silicon IP is a key building block for this methodology, as it frees the designer from details of standard block's configuration in order to concentrate on design features which differentiate the product.
In the end
A stable and profitable system needs all partners to continually invest in future rewards. Everyone participated in disaggregating the previously established infrastructure for cost and/or profit reasons, not realizing or expecting the full impact of our decisions. Yes, we willingly opened Pandora's box and we must work together to create long-term business models (hybrid royalty/license fee) along with establishing standards and criteria to enable IP to improve the likelihood of quickly and profitably completing the constantly growing puzzle.
The topic of IP is not to be taken lightly. I would encourage all to be involved and help drive toward design standards. These evolving standards may change perceptions or lead to the adoption of new tools and metrics that quantify IP alternatives. Quality is the result of a well-defined design process systematically followed. Folklore and axioms are cheap. GSA's IP Portal is accessible to all and contains ideas, information, and tools to help successfully navigate your IP needs. The portal can be accessed at: http://www.gsaglobal.org/ip/index.aspx.
| Author Information |
 Bill Martin has over 25 years of experience in consulting, product design, and project management. He joined Mentor in 2000 and has held senior roles in Mentor Consulting and IP. In addition to Mentor, he previously worked for Synopsys, VLSI Technology, and Mostek. Martin holds an MBA from the University of Texas at Dallas and a BS in computer engineering from the University of Illinois, Urbana. He has been granted five patents.
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