Cadence offers low-power-methodology kit
By Michael Santarini, Senior Editor -- EDN, May 15, 2007
Building on its thrust into the low-power-design area and leveraging its CPF (Common Power Format), Cadence Design Systems is now announcing a low-power-methodology kit. Until recently, low-power-design has been the responsibility mainly of specialists and low-power-design gurus. However, starting at the 130-nm process node, the transistors fabs employed to increase the performance of their silicon processes came with a nasty side effect: static leakage. That is, high-performance transistors leak power even when they are not in use, which wastes power in wired-system applications and more quickly drains battery life in wireless-system applications. Therefore, most designers, not just specialists, working with new processes must employ low-power design techniques. For that reason, Cadence has for the last couple of years been diligently working on low-power approaches, says Neil Hand, director of vertical-solutions marketing at the company.
Two years ago, the company started developing CPF with partner companies and ensuring that most of its digital-tool flow could use CPF to help digital-IC-design customers better create low-power designs.
This year, Cadence introduced some of the fruits of that labor when it officially released its Low Power Platform, in which its Encounter RTL-to-GDSII (Graphic Design System II) flow and its Incisive verification tools all now support low-power design through the CPF. Now, the company is trying to increase adoption of its low-power format and help mainstream designers deal with low power by offering the Low Power Methodology kit—essentially, a bundling of tools, IP (intellectual property), reference designs, and training. Cadence also offers similar kits for AMS (analog-mixed-signal), verification, and RF-SIP (system-in-package) design. “This is building off the previous design kits and bringing together a mix of methodology, best practices, automation, and IP to speed adoption of low power across functional groups and customers of all experience levels and to make it easier for customers who have never touched low power before to get up and running and produce high-quality designs as soon as possible,” says Hand.
To help design groups get started, Cadence has developed a general reference design it calls a segment-representative design to illustrate the blocks and segments in a typical design that require low-power optimization. Supporting this approach, Cadence has built modularized design-flow structure that illustrates the tools required during each phase of the design, including logic synthesis, functional verification, design for test and ATPG (automatic-test-pattern generation), physical design, formal implementation verification, and power-grid sign-off. The Low Power Methodology kit also includes a list of IP for low-power design and all the tools that Cadence offers for a low-power flow: Incisive Enterprise Manager, Incisive Enterprise Simulator, Incisive Design Team Manager, Incisive Design Team Simulator, Incisive Formal Verifier, Encounter RTL Compiler, Encounter Test, First Encounter, Encounter Conformal Technologies, SoC Encounter, and Voltage Storm. Hand says that the tool flow in the kit is modular so that customers can incorporate non-Cadence tools into the flow if they wish. If customers use a pure Cadence flow, he says, they will see greater benefits in tool interoperability.
Customers who purchase the kit will also receive five days of applicability consulting and can purchase more training or consulting as required. The starting price for the kit is $30,000.
