Networking-SOC case study: Conservative architecture, aggressive process
While some IC architectures migrate smoothly to new CMOS process geometries, others require complete revision.
By Ron Wilson, Executive Editor -- EDN, April 19, 2007
As the performance benefits of new CMOS process geometries become more and more tenuous (see, for instance, "TSMC talks details on the meaning of 45-nm CMOS"), designers are finding that system architecture is playing an increasing role in process decisions. An architecture that made perfect sense at 130 nm may need to be completely revised for each new process node. Conversely, some architectures prove inherently easy to migrate and benefit more from a new process.
Chuck Gershman, CEO of Bay Microsystems, suggests that the architecture used in the company's Chesapeake network-processor chip provides a case in point. Whether this was a matter of brilliant forethought or serendipity is unclear. But the chip makes an excellent case study in the interactions between architectural decisions and process strategies.
Gershman offers a rough classification of network-processing architectures into two broad categories: those that have pursued microprocessor, or microprocessor-like strategies, and those that have used the much older signal-processing strategy of a pipelined architecture with function-specific stages.
As line rates have grown, Gershman suggests, those using Intel-architecture CPUs, network-processor chips, or embedded microprocessor cores have had only one choice: multiprocessing. These designers simply could not increase clock frequency enough for a single CPU to keep up with packet-processing rates that will reach 150 million packets/sec at 100 Gbps line rates. The only alternative, as Intel has noisily concluded in the server world, is to increase the number of processors.
But unlike in the PC or server worlds, where this increase tends to stop in well-understood territory—four or eight CPUs—the number of processors necessary for 100 million packets/sec is on the order of tens or even hundreds, Gershman maintains. This has led companies to create massively parallel chips that go well beyond the state of the art in interconnect architectures and in tools for modeling resource contention.
The alternative approach, the pipeline, has its own advantages and disadvantages. The obvious disadvantage is that architects must be elegantly careful about flexibility. The world of IP-packet processing has become complex on an almost fractal scale. When the processing of a particular kind of packet in a particular environment falls outside the domain implicitly created by the pipeline's designers, troubles accumulate quickly, exacting a price in die area and performance.
The only apparent solution to this problem is a combination of a deep understanding of packet-classification technology and very clever design of somewhat-programmable pipelines. Not only must the pipeline stages appear in just the right order to avoid having to recirculate packets, but each stage must also have just the right combination of hard-wired performance and programmable flexibility. Else the whole thing devolves into a cluster of quasi-CPUs within a very limited interconnect topology.
It's a challenging problem, but it has its rewards, according to Tony Chiang , Bay's senior vice president of engineering. The seasoned chip designer points out that one of the most valuable attributes of pipelined architectures is that they reduce the necessary system clock rate. When Bay began designing the current Chesapeake offering, the company's existing product was done at 130 nm. To reach the target packet-processing rate for the next chip, the company began looking at 90-nm processes. "We looked at other companies doing 90-nm designs," Chiang says. "It was a nightmare. So we looked closely at our maximum pipeline-frequency requirements, and concluded that we could meet them with a 110-nm process node."
In fact, according to Gershman, the design was done at 110 nm with a relatively relaxed COT (customer-owned tooling) design flow requiring no custom design work. The internal operating frequency of the pipeline stages is 367 MHz, and the pipeline itself clocks once for every three internal clock cycles, or at about 120 MHz.
Architectural studies for a projected 100-Gbps chip suggested that, with a change in clocking strategy, the pipeline could meet the packet-rate specifications at 700 MHz. "That requires us to resynthesize the RTL, and in some cases where we don't meet timing on a node, to push out another pipeline stage," Chiang said. "But it's nothing like the pain of trying to make a chip run at 2 or 3 GHz."
The relatively relaxed frequency allowed Chiang to take another powerful risk-management step. "The big design risks were not in the RTL," Chiang explains. "They were confined to a few specific areas—the memory compilers, the SerDes blocks, PLLs and high-speed I/O pins. By establishing a rigorous intellectual-property-selection process, we were able to export this risk to specialized IP vendors who had the experience to deal with it."
The evaluation process included reviewing design and margin calculations with the IP vendor, then working with that vendor in detail during the integration process. Chiang's team attempted to first bound and then explicitly manage the design risks. So instead of a design roadmap that calls for multiple test chips at a new process node, Bay leaves that work up to its IP vendors and their shuttle runs. This time around, the company plans the first tapeout to be the full-chip design.
Ironically, this conservative approach—using the architecture to limit clock frequency and hence the challenges of meeting timing in a process with high variations, and using IP vendors to minimize risk from blocks that cannot be pipelined—has led Bay to a more aggressive process strategy this time around. Rather than migrating from 110 nm to 90 nm, the company is planning its next tapeout for 65 nm.
Several facts led the company to believe the move will entail relatively little risk: 65-nm foundry processes have stabilized very quickly, advanced IP vendors already have silicon in these processes, the processes support existing tools, and the 700-MHz spec is nowhere close to the edge of the envelope for 65 nm. The choice offers potentially big rewards in die area, as well as the opportunity to spend engineering resources on reducing power consumption rather than on meeting timing.
It all goes back, Gershman would insist, to the pipelined architecture.
