Thread or die: EDA must lead, or get out of the way of Moore’s Law
By Isadore Katz, CLK Design Automation -- EDN, May 21, 2007
The most important opportunity and challenge for EDA is to stay ahead of design requirements. Our software has to scale at the same rate as the designs themselves. When designs grow from 1 to 10 to 40 million placed instances, we must keep pace.
While new languages and automation can increase design productivity, in the end we still generate transistors that get printed on silicon. Physical layout, parasitic extraction, and signal integrity are all done at a granular level that mandates scaling in throughput and capacity.
For the past 20 years, EDA tools have followed Moore’s Law. By porting to 32- and then 64-bit architectures and moving from proprietary platforms to UNIX and Linux, Moore’s law delivered faster and bigger computing platforms. EDA developers felt free to focus on algorithms and let the hardware carry the performance burden.
The free ride is over. Processors no longer double in speed every two years, and EDA tool run times are not keeping pace. Users routinely report order of magnitude increases in run times where tasks that used to take hours, now take a week. Moore’s Law, which used to deliver reliable increases in performance, is now working against us.
There are two solutions to this failure to keep pace: threading and incremental. Threading is step one: distributing the work - all of the work - to as many processors are as available in a computer. Incremental is the second: only optimize or re-calculate the minimum amount necessary, and give exactly the same answer (or as good a solution) as if the entire design had been re-evaluated.
Threading is where it has to start. While individual processors are not speeding up at the rate they once did, there are a lot more of them per computer. From multi-core CPUs to multi-CPU platforms, the available compute power is actually growing faster than at any time in the past 10 years.
With proper threading — where every activity from reading in data to writing out results is addressed — we can actually can lead Moore’s law. The latest solutions coming to market have demonstrated linear threading through 16 processors, theoretically all the way through 64 processors. The result is that a task such as full signal integrity analysis now takes less than an hour as compared to the 20 hours it takes with existing tools.
The other half of the equation is incremental analysis. Today, shifting one wire can result in a 24-hour extraction and signal integrity analysis on a massive server. Even using threading to reduce run time to an hour is unacceptable. With hundreds of potential changes, there are not enough hours in the day. Design time has to be proportional to the change made. With true incremental analysis, designers can make modifications and get answers back in seconds that are as accurate as if the full design has been run. Incremental analysis radically changes the rules of the scaling game; we are getting out of the way of Moore’s law.
The question is how to get to an incremental and threaded solution. Trying to thread existing software is a losing proposition. At best, this approach works with three or four processors. In fact, the software actually slows down when applied to five or more processors. Moreover, the threading is never applied to the entirety of the program. The “high-pole in the tent” simply shifts to another section of the software. What value is there in having a 16-core server, if most of the cores are idling?
The same holds true for incremental. There are many sorry stories of attempting to take batch software programs and make them “incremental.” The restrictions, inaccuracies and limitations of this approach make it unusable.
What is needed is a bottom-up, new architectural initiative for every tool in the design implementation flow. There is no other way to deliver software that continues to scale as more processors get packed into one computer, or that makes run times proportional to the size of an incremental change. Then, EDA can get out in front of Moore’s Law, which is where we need to be.
Isadore Katz is president and CEO of CLK Design Automation andhas over 20 years of experience in executive management, marketing and product management in the EDA software and components industry. Previously, Katz was CEO and president of Lightchip, a supplier of component and software solutions to the telecommunications and cable industry, and Chrysalis Symbolic Design, an EDA provider of formal verification solutions to the semiconductor and electronics systems industry. In addition, Katz has held executive positions at Cadence Design Systems, MetaSoftware and Dataquest. He holds a Bachelor of Arts from Wesleyan University and Masters degree from the Sloan School at MIT.
