Xilinx optimizes Virtex-5 for high-performance DSP apps
By Ann Steffora Mutschler -- EDN, February 5, 2007
San Jose-based programmable logic leader Xilinx Inc. said today initial shipments of its 65nm Virtex-5 SXT field programmable gate arrays (FPGAs) optimized for high-performance digital signal processing (DSP) are now available.
Xilinx is claiming its SXT platform allows performance of 352GMACs at 550MHz, while consuming 35 percent less dynamic power as compared to previous 90nm generation devices, and is the first DSP-optimized FPGA family to integrate serial transceivers.
The Virtex-5 SXT platform joins the company’s XtremeDSP products with three new device options aimed at the ultra-high DSP bandwidth and lower system cost requirements of next-generation wireless and video applications.
Further, the company says the Virtex-5 SXT platform aims to deliver the highest ratio of DSP blocks-to- logic needed for high-performance digital signal processing applications in wireless, such as WIMAX and high-definition video, such as surveillance and broadcast.
As such, the enhanced DSP slice (DSP48E) includes a 25x18-bit multiplier, a 48-bit second stage for accumulation and arithmetic operations, and a 48-bit output that can be expanded to 96-bits. The wider data path and output enable increased dynamic range and higher precision as well as optimized support for single precision floating point operations using half the resources consumed by 90-nm FPGAs.
The DSP48E slice also includes integrated cascade routing enabling parallel processing at full 550-MHz speed, delivering an industry-leading 352 GMACs of DSP performance using the 640 DSP48E blocks available in the largest Virtex-5 SXT device. Additional capabilities include an independent C register and an expanded second stage with support for SIMD operations and pattern detection for more efficient DSP implementation.
The SXT platform is also targeted at the ever-increasing I/O bandwidth requirements of high-performance DSP applications with up to 16 low-power 3.2Gbps RocketIO serial transceivers that support industry-standard protocols such as CPRI/OBSAI, HD/SDI, Serial RapidIO, PCI Express and Gigabit Ethernet specifications among others. PCI Express and Gigabit Ethernet standards are supported with built-in protocol blocks and interfaces.
Manufactured on 65nm triple-oxide technology, the Virtex-5 SXT platform is meant to reduce overall dynamic power consumption by as much as 35 percent and maintain a low static power consumption, making it well-suited in defense and public safety applications that require longer battery life, such as handheld software defined radios.
Also, the enhanced DSP48E block consumes only 1.4mW/100MHz typical at 38 percent toggle rate, and the Virtex-5 RocketIO transceivers consume as little as 100mW typical at 3.2Gbps, all of which combine to lower the overall system power and cost.
The Virtex-5 SXT devices range in logic density from 35,000 to 95,000 logic cells and have 192 to 640 dedicated DSP48E slices, providing the highest level of system integration that enables developers to select the right mix of features to optimize overall system cost. These devices also offer the highest memory-to-logic ratio for efficiently implementing memory-intensive functions in video processing and medical imaging with up to 10.3MB of memory offering maximum aggregate bandwidth of 58 Tera-bits/sec.
Virtex-5 SXT engineering samples are now shipping for the mid-range SX50T device, with smallest SX35T and largest SX95T devices to follow over the next four months.
The SX50T device will list for $299 in 1,000 unit volumes by the second half of 2008.
Omid Tahernia, VP and general manager of the processing solutions group at Xilinx concluded in a statement, “Our new Virtex-5 SXT platform effectively changes the industry’s traditional view of DSP by providing higher algorithm performance, better power efficiency and lower system cost for a broader range of high-end applications.”
