45-nm, multicore microarchitecture targets communications platforms
By Robert Cravotta, Technical Editor -- EDN, July 12, 2007
Freescale structured its next-generation multicore platform on a scalable on-chip fabric that supports concurrent, nonblocking connectivity for as many as 32 heterogeneous processor cores with application accelerators and a trilevel-cache hierarchy that supports 100%-hardware-based cache coherency. The platform will initially center on an enhanced 1.5-GHz Power Architecture e500-mc core, based on the e500 core, with back-side L2 caches for each core, multiple L3 shared caches, and multiple memory controllers. The on-demand application accelerators include pattern matching, decompression, cryptographic security, table look-ups, and datapath-resource management to handle intrachip message passing and memory-buffer reservation.
The multicore platform will use a “hypervisor” environment to support multiple individual operating systems that can safely share system resources, including processor cores, memory, and other on-chip functions. Freescale plans to offer the first product it based on this platform for sampling in late 2008; however, a Virtutech simulation environment is available now using Freescale’s current-generation multicore MPC8572E and MPC8641D processors. The simulation environment for Freescale’s new multicore platform will be available in the fourth quarter of 2007.
