Sigrity introduces cost-savvy power-decoupling-capacitor tool for PCB and package design
By Michael Santarini, Senior Editor -- EDN, March 12, 2007
[Click for larger image] |
One of the longest running problems in PCB (printed-circuit-board) design has been trying to figure how much decoupling capacitors you need for your design. PCB engineers often use too much decoupling capacitance to ensure that their designs will achieve power stability requirements of their system and still meet performance goals. But each decoupling capacitor adds extra cost to the design, and typical designs have a lot of unnecessary capacitance.
Addressing this problem, Sigrity Inc recently introduced a smart decoupling-capacitance tool that helps users place just enough capacitance in their designs to reduce costs and still meet performance goals. The company’s new OptimizePI targets PCB and package decoupling capacitance (see figure). The tool’s inputs are a user-customizable library and the layout of the design. Users select the best candidates for their designs from the library and then direct the tool to analyze the layout. “The tool selects at each location what is the best capacitor they should choose from the library,” says Jiayuan Fang, president of Sigrity. “The tool does a large-scale statistical analysis and automatically tries a lot of schemes. The tool then automatically places the appropriate decoupling capacitance where it is needed on the board based on performance and cost constraints. Given target performance, this tool will automatically find what is the lowest cost.”
The tool has a what-if capability that allows users to test capacitors for the right balance of performance and cost. “It adds a new dimension of automation for because you are able to stabilize your power-delivery system and achieve a performance level at a much reduced cost,” says Teo Yatman, vice president of business development.
Sigrity licenses OptimizePI for a $35,000 annual subscription. That price may seem high for a typical PCB tool, but Fang says the price point is in line with analysis-class PCB tools and that the cost is reasonable if you take into account the amount of savings your design project will gain from avoiding the overuse decoupling capacitance. Fang claims that some beta users of the tool cut capacitance by 50%, drastically reducing the overall cost of their product and saving board space. “If you save even 20 cents for a volume product, that is, say, 20 million units, you’d save $4 million,” says Fang.
Fang also claims that, because the tool is highly automated, you need no power-integrity-engineering expert to run it. He notes that designers can use the tool during several steps in the PCB- and package-development process. For example, they can use it during design to figure out the lowest cost configuration and to get a better idea of open board real estate, during layout to implement the best configuration after placing the other components in the design, and even during manufacturing if other more inexpensive units become available or if a previously targeted unit becomes unavailable.
