Cadence debuts 65-nm reference flow targeting Common Platform
By Colleen Taylor, Contributing Editor -- EDN, April 23, 2007
San Jose, Calif.-based EDA player Cadence Design Systems Inc. today announced the immediate availability of the 65-nm Common Power Format (CPF) enabled reference flow targeting the Common Platform technology.
The company said that its new reference flow is the next step in the ongoing collaboration between Cadence and the Common Platform coalition comprised of IBM, Chartered Semiconductor Manufacturing and Samsung.
The Common Platform members align their manufacturing for synchronized production across 300-mm fabrication facilities at 90-nm, 65-nm and 45-nm process technologies.
At the group's core is the idea that a single design can be multi-sourced to any of the group's facilities, essentially making it possible to produce nearly identical chips from any one of several manufacturing facilities. The group's most recent additions as design enablement partners have included Freescale Semiconductor and Qualcomm.
Cadence said it worked closely with the Common Platform technology partners to develop its new 65-nm flow. It is based on the Cadence digital IC design platform including the company's Encounter timing system and CPF. The flow is aimed at accelerating time to market for low-power system-on-chip (SoC) designs, Cadence said. The RTL-to-GDSII flow claims to address design challenges from chip prototyping through power, timing and area optimization and is targeted for wireless, wireline and consumer applications. ARM's Metro low-power IP is also an integral component of the reference flow, Cadence said.
The new 65-nm design reference flow is available immediately, Cadence said. Its reference flow kit contains a reference design, documentation and scripts to run the reference flow.
