Altera moves to ease serial-bus-interconnect issues on boards
Arria GX offers low-cost bridge for PCI Express, Gigabit Ethernet, and SRIO.
By Ron Wilson, Executive Editor -- EDN, May 8, 2007
As boards have become more congested and the volume of data moving between chips has grown, the traditional approach of simply extending a CPU parallel bus to the other major chips on the board has broken down. Led, perhaps, by Intel's reliance on PCI Express (PCI-E) and Texas Instruments' use of serial RapidIO (SRIO) for board-to-board and, increasingly, onboard interconnect, designers are beginning to consider high-speed serial links as the most effective way to move large volumes of data between chips. Gigabit Ethernet, coming from heavy use in communications backplanes, is also getting consideration in that area.
But the use of high-speed serial interconnect at this level is also creating problems, as many design teams have already discovered. Not all CPUs, DSPs, and ancillary chips come with interfaces for the desired buses. Bridges may be necessary between conventional parallel interconnect and the serial links. And electrical design, especially in the area of signal integrity, can be too great a challenge for teams that are not staffed to handle it.
Altera has offered some help by providing LVDS (low-voltage differential signaling) I/O and high-speed serial controllers in its Stratix GX family. This allows designers to use a single, big programmable part as both a bridge and a repository for control and computing functions. But even the small Stratix GX devices are too expensive for the shallow budgets of many designs. And with their system-on-chip orientation, they represent overkill on logic and memory resources.
David Greenfield, Altera's senior director of product marketing, says that the combination of the need for design simplicity and the need for low cost has driven Altera to develop an entirely new family to address the serial-bus interconnect issue. Like Stratix, the new Arria GX family will have LVDS transceivers, support for PCI-E, SRIO, and Gigabit Ethernet, as well as for DDR 2 memory ports (view block diagram). But these features will be built on a smaller, less-expensive platform.
The architecture achieves cost savings in a number of ways, according to Greenfield. One is simple conservatism—using an existing 90-nm process and die sizes to construct devices that will offer from four to 12 transceiver channels, from 21,580 to 90,000 equivalent logic elements, and from 1 Mbit to 4.5 Mbits of memory. The platform also includes DSP blocks. So while the parts are not huge by modern FPGA standards, they do have more than sufficient resources to gather up some coprocessing and control functions as well as bus-bridging functions. The Arria GX devices are compatible with existing Altera soft IP (intellectual property) cores, including the Nios CPU. Some cores have been reoptimized for use in the new family.
A reasonable question, Greenfield says, is why Altera didn't simply add transceivers to the existing Cyclone line. The answer is quite simple: Cyclone is in wire-bond packaging. "If you put one high-speed serial port in a wire-bond package, it would probably be fine," Greenfield says. "If you combine several ports, maybe add in a DDR2 DRAM port and some computing capability, a design team is going to have to do very careful package-simulation runs to make sure they aren't going to have problems with ground bounce, supply voltage sag, and lead inductance. We felt that simplicity of design dictated against the use of wire-bond packaging."
Similarly, Altera has tried to make board-level analysis as simple as possible. The serial ports will only be available at 1- or 2.5-Gbps speeds, and changes to the soft-IP protocol engines that would enable a proprietary bus mode are locked out of the design-tool user interface. So Altera is reasonably comfortable that the chips have been designed to operate within margins on a worst-case logic design and layout. And the board designs should stay manageable.
Not that anything can make board design with serial interconnects into a turnkey affair. "The lower the speeds, the less analysis the board designers are going to have to do," Greenfield says. "Below about 1 Gbps you can use IBIS models. Above that, maybe you want more detailed HSPICE modeling. But there is no way you can avoid modeling the board if you want to understand what is going on."
Recognizing that not all design teams will have this expertise or infrastructure, Altera is reinforcing its FAE (field applications engineering) organization in preparation for the new product. For some time now, according to Greenfield, the company's first-tier FAEs have been supporting high-speed serial designs using the Stratix-GX family. The company is now broadening that base of support to more of its FAE organization, and actively working with distributors and ODMs to try to ensure a first-time-happy experience for smaller teams moving to this technology.
Shipping will start in June for the first members of the family, with prices as low as $50 each in 25,000-unit quantities. The version 7.1 release of Quartus II supports the parts.
