Gain-of-two sample-and-hold amplifier uses no external resistors
If the required voltage gain of a sample-and-hold amplifier is an integer, this circuit achieves a gain of two without using any power-dissipating external resistors.
Marián Štofka, Slovak University of Technology, Bratislava, Slovakia; Edited by Charles H Small and Fran Granville -- EDN, November 8, 2007
When you need to simultaneously sample a signal and amplify the signal level, you can cascade a common gain-of-one sample-and-hold amplifier and an amplifier with a voltage gain of one. With some exceptions, such an amplifier has two external resistors (Reference 1). These resistors dissipate power even at the steady state of the sample-and-hold amplifier. In monolithic ICs, power dissipation and the consequent generation of heat from resistors are not the only items in the list of the drawbacks of external resistors. Integrating precise resistors within a silicon chip requires more processing steps, because such resistors are thin-film NiCr (nickel-chromium) or SiCr (silicon-chromium) elements. Manufacturers laser-trim these resistors to a tight tolerance value, contributing to the cost of an IC. Because these resistors occupy more chip area than standard signal-processing transistors, the chip must be larger, further increasing the final cost. It’s no wonder that designers of monolithic ICs as much as possible avoid using precision resistors.
If the required voltage-gain of a sample-and-hold amplifier is an integer, which it is in most cases, you can use an alternative way of increasing the magnitude of the output signal. For a voltage gain, G, the circuit can simultaneously track input voltage, VIN, on temporarily ground-referenced tracking capacitors. Subsequently, an interruption occurs in tracking and cancels the ground referencing of G–1 of these capacitors. Meanwhile, the tracking capacitors stack on top of each other. The voltage on the stack is the sum of voltages of all of these capacitors, and it thus has the value of GVIN. Upon the sample command, the constant voltage of GVIN gets stored in the G+1 ground-referenced storing capacitor.
Figure 1 shows an example of a sample-and-hold amplifier with a voltage gain of two. Voltage followers control the potentials on capacitors C1, C2, and C3 using their shutdown function. The design uses Analog Devices’ AD8592 dual op amps because their output-leakage current in shutdown mode can be lower than 10 pA (Reference 2). You can follow the operation of the sample-and-hold amplifier with the timing diagram (Figure 2). The external logic-control signal, QS, is at a low level, and the C1 and C2 capacitors simultaneously track the voltage at its input. The shutdown inputs of followers A1, B1, and A2 are tied together. At 
=high, they are enabled, so the input voltage appears at the outputs of A1 and B1, and no voltage appears at the output of A2. After the high-to-low transition of , a dead slot follows with each of the controlled followers turning off. At Q=high, B3 and B2 turn on. Thus, the voltage in C2 appears at the output of B3. The potential of the input voltage occurs, therefore, at the lower node of C1 (Pin 2 of IC2). Because C1’s voltage has the same value as the input voltage and the output voltage, the B2 follower is 2VIN. Capacitor C3 thus charges to the voltage of 2VIN. After the high-to-low transition of QS, another dead slot follows to prevent any cross-conduction in the circuit. At the next high-to-low transition of QS, the process repeats.
The A3 follower serves as an impedance converter, outputting the voltage in C3. The single NOR and AND gates, together with op amp IC6 functioning as a delay line, modify the single external-logic-control signal to create the properly timed internal logic signals, and QS.
For a noise analysis, assume that the noise characteristics of each of the followers are the same—namely, the standard deviation, σA, of the random component of the output voltage of a single follower. At the end of the tracking interval, both C1 and C2 charge to the input voltage. The standard deviation of the VC2 voltage is σA only for the A1 follower. The standard deviation of VC1 voltage is, however, 
because C1 charges through two series-configured followers, B1 and A2. The standard deviation of VC1+VC2 voltage thus has the value of 
The voltage of VC1+VC2 applies to C3 through two followers in a cascade, B3 and B2, within the sample interval. Further, the VC3 voltage applies to the output through the A3 follower. Because all of the noise sources are mutually independent and because they all effectively act in series, the standard deviation of the output voltage is σOUT=
Increasing the integer gain to the value of G yields 
You now pose an RSNR (relative signal-to-noise ratio) as gain, G, over a relative increment of noise at the output, yielding:
For the sample-and-hold amplifier in Figure 1, the RSNR equals 0.8165, meaning that the noise characteristics of the circuit are slightly worse than those of a single follower. For a gain of three, the RSNR has the value of one, and, starting from a gain of four, at which the RSNR is 1.155, it gradually rises with increasing gain. The conclusion is that, for voltage gains of four or higher, the noise characteristics of the sample-and-hold amplifier are better than those of a single follower.
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