Toshiba validates 22-nm CMOS imprint litho
By Ann Steffora Mutschler, Senior Editor -- EDN, October 16, 2007
Japanese semiconductor giant Toshiba Semiconductor Co. reported today that it has validated the use of imprint lithography technology from high-resolution nano patterning imprint system supplier Molecular Imprints Inc. (MII) in the development of 22-nm CMOS devices, and has fabricated narrow trench features at dimensions down to 18-nm.
Toshiba, which presented its findings in a paper at the 33rd International Conference on Micro- and Nano-Engineering in Copenhagen, Denmark last month, detailed the process capability and stability of MII’s Step and Flash Imprint Lithography (S-FIL) technology for next-generation semiconductor manufacturing.
Specifically, Toshiba has confirmed enhancements over earlier performance in the areas of imaging, defectivity and overlay control; the company used MII’s Imprio 250 system to pattern 18-nm isolated features and 24-nm dense features with smaller than 1-nm critical dimension uniformity (CDU) and less than 2-nm line edge roughness (LER). Defectivity levels of as low as less than 0.3 defects per square centimeter were achieved, which approach immersion lithography defectivity levels. Device overlay results were also within Toshiba’s required specifications, the company noted.
Mark Melliar-Smith, CEO of MII said the results, along with similarly strong tool performance findings from another leading chip manufacturer, further confirm the performance of the Imprio 250.
“Unlike extreme ultraviolet lithography, our technology builds on the existing optical lithography infrastructure -- helping to make it ideally suited for the economic production of very-high-density CMOS devices,” he added in a statement.
MII believes its S-FIL technology is a viable solution for critical device layer applications at the 32-nm node, and a superior solution at and beyond the 22-nm node.
