Intel on Schedule with 45nm
By Ann Steffora Mutschler -- EDN, December 1, 2006
Since demonstrating fully-functional SRAM memory chips at 45nm, Santa Clara, Calif.-based semiconductor industry leader Intel Corp. has checked off the milestones one-by-one, this week confirming with Electronic News that it is well on track to achieve shipments of its 45nm “Penryn” chips in the second half of 2007.
Intel technology analyst Rob Willoner said this week during a one-on-one interview that as the 45nm process ramps up on the D1D fab in Oregon, the company is transitioning another one of its 90nm fabs to 65nm – bringing the number of fabs at 65nm to three.
Willoner also filled in some process details on Intel’s 65nm process. To achieve energy-efficient transistor performance, Intel uses Silicon Germanium (SiGe) that allows NMOS drive performance of 1.21mA/um and PMOS drive performance of 0.71mA/um at 1.0Volt and 100nA/um leakage.
Also, Intel said its 65nm process allows scaled dimensions as follows: gate oxide, 1.2nm; gate length of 35nm; transistor pitch of 220nm; metal 1 pitch of 210nm; metal 2 pitch of 210nm; metal 3 pitch of 220nm and an SRAM cell size of 0.62 square microns.
Advanced process nodes have driven multiple core chips given the ability to pack more transistors on a chip, of a smaller size and of greater transistor performance.
“Within two or three years, all microprocessors will be multi-core,” Willoner noted.
The Penryn family processors were designed specifically for the 45nm process node and build on the performance and energy-efficiency of Intel’s Core 2 and Xeon processors. These chips are aimed at server, desktop, and mobile-optimized versions including second-generation quad-core chips.
Penryn also contains Stream SMDE Extension (SSE) 4 instructions that specifically address high-performance computing applications.
Initial Penryn chips are expected to come out of the fab any week now, Willoner concluded.
