Virtex-5 adds PCI Express and 10-Gbit-Ethernet cores
By Michael Santarini, Senior Editor -- EDN, October 18, 2006
Xilinx has released the second platform derivative of its Virtex-5 FGPA family targeting markets requiring serial connectivity. Xilinx this year also unveiled its top-of-the-line Virtex-5 FPGAs, the first FPGAs in the industry at the 65-nm node. The new devices feature a six-input-look-up-table architecture and some design and foundry tricks to keep power consumption on par with the company's 90-nm Virtex-4 FPGAs and still gain the usual performance and price-per-gate advantages of process reductions. When Xilinx announced the family, the company also released the LX base platform, which is a pure-logic, sea-of-gates FPGA. Now, the company is releasing derivative platforms of the Virtex-5 targeting specific markets.
The first of these derivative platforms, the Virtex-5 LTX (Picture) includes a lot of logic, as does the LX, but adds several hard blocks of serial I/O to help designers targeting the "triple play"—video, data, and voice—for markets requiring serial connectivity. Balaji Thirumalai, senior manager of Virtex marketing at Xilinx, says that designers in the wired- and wireless-communications market have been the traditional targets for these types of devices, but triple-play serial connectivity is now starting to displace parallel connectivity and is making its way into other applications, such as consumer electronics, audio/video broadcast, automotive, aeronautics and defense, storage, and servers.
"We introduced serial I/O in Virtex II Pro and Virtex-4, and, over the years, customers became comfortable with having FPGAs with SERDES (serializer/deserializer) features," says Thirumalai. "Those customers were typically in the communications and networking areas and willing to take risks with leading-edge technology. They wanted the highest performance and data rates. Now, as the mainstream market starts to adopt serial rather than parallel I/O, the market has slightly different needs." The biggest difference, says Thirumalai is that most of the mainstream applications don't call for blistering fast I/O and are typically operating at speeds of less than 3.2 Gbps.
Xilinx claims that LTX helps designers target applications in this sweet spot. Thus, it integrates PCI Express and Ethernet MAC (media-access-controller) hard cores into the fabric. The hard cores include RocketIO transceivers, which give the LTX speed as great as 3.2 Gbps with typical power consumption of 100 mW. The LTX Ethernet support includes four independent 10/100/1000-Mbps blocks that work with RocketIO transceivers, and the PCI Express support includes a PCI Express endpoint block that works with the RocketIO transceivers to give users access to one-, two-, four-, and eight-lane PCI Express interfaces. With those blocks, the LTX can support PCIe, Gigabit Ethernet, XAUI (extended attachment-unit-interface), and OC-48 protocols, among others. The company initially released the 5VLX30T, 5VLX50T, and 5VLX110T LTX versions, which have 30,000, 50,000, and 110,000 look-up tables, respectively.
The company is offering sample silicon of these devices and plans full production for early 2008. The company also plans to offer an 85,000-look-up-table LX85T and 330,000-look-up-table LX330T. In 2008, the LX30T, LX50T, and LX110T devices will sell for $109, $189, and $529 (1000). The next platform on the company's Virtex-5 road map adds a DSP as well as serial I/O to FPGA logic. Xilinx plans to announce that device during the first half of next year
