Apache option adds support for advanced low-power techniques
By Michael Santarini, Senior Editor -- EDN, May 8, 2007
EDA vendor Apache Design has added an optional module to its low-power-design tool, RedHawk-LP (low power); the new module, RedHawk-ALP (advanced low power), adds support for emerging low-power design techniques. Redhawk-LP, which Apache introduced last year, supported low-power techniques, such as power gating and MT (multithreshold)-CMOS design. RedHawk-ALP adds support for VT (variable-threshold)-CMOS circuits with substrate back-biasing, power-gated memories, and custom macros, and on-chip low-dropout-voltage regulators.
When they add the ALP option to Redhawk-LP, users can back-bias a substrate with VTCMOS circuits, thus lowering leakage. Dynamically altering substrate voltage can add noise to the supply source and create variability problems. To address this problem, ALP allows users to extract bias networks and analyzes full-chip dynamic power integrity for trade-off analysis. The tool also comes with modeling capabilities and increased simulation support for users employing the power-gating/MTCMOS technique on memories. Traditionally, designers have used the technique on the logic portions of the design. But they now employ it on embedded memories in SOCs (systems on chips).
Many advanced SOCs today incorporate multiple “voltage islands,” or sections with different voltages. For many of these designs, users place the low-dropout voltages on-chip, rather than use an external chip. However, because these voltages are an analog function, they tend to be somewhat temperamental. Thus, designers have traditionally used slow SPICE to simulate their behavior or used ideal voltage sources, which don’t account for the power noise that low-dropout circuit generates. The ALP accurately models low-dropout circuits and gives users a true look into their impact on the rest of the SOC. The price of the RedHawk-ALP starts at $330,000.
