Toshiba, Rambus Ink Another License Deal
By Colleen Taylor -- EDN, October 11, 2006
Toshiba Corp. has inked a license agreement for Rambus Inc.'s XDR memory controller interface cell, dubbed XIO, and the Rambus PCI Express Gen 1 PHY cell. The Rambus interface solutions will be implemented in Toshiba's 65nm process technology for integration into the company's latest consumer, computing, and communications applications.
Rambus touts its XIO memory controller as the high-performance, low-latency interface to Rambus' XDR DRAM. The controller is tailored for graphics-intensive applications in consumer electronics and computing, Rambus said, as a single, 2-byte wide, 3.2 GHz XDR DRAM component provides 6.4 GB/sec of peak bandwidth.
Rambus said the XDR memory architecture features four key enabling technologies:
--Differential Rambus signaling level (DRSL), low-voltage, low-power, differential signaling standard that enables scalable multi-GHz, bi-directional, and point-to-point data busses that connect an XDR memory controller (XIO) to XDR DRAM devices.
-- Octal data rate (ODR), a technology that transfers eight bits of data on each clock cycle, four times as many as today's state-of-the-art memory technologies that use DDR (double data rate) clocking.
--FlexPhase, a circuit technology that enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock.
-- Dynamic-point-to-point (DPP), an innovation that maintains the signal integrity benefits of point-to-point signaling on the data bus, while providing the flexibility of capacity expansions with module upgrades.
"This agreement continues the long and successful collaboration between our companies to provide state-of-the-art technology for today's most demanding computing and consumer electronics products," Laura Stark, senior VP of platform solutions at Rambus, said in a statement.
Toshiba and Rambus have a history of collaboration. In July, the companies inked a similar agreement giving Toshiba licesne to use Rambus patents for SDRAM and DDR SDRAM memory controllers.
