Toshiba expert discusses future of flash technology
Although optimistic about the short-term viability of NAND flash technology, a Toshiba executive believes that at some point a new storage mechanism will have to take over for conventional cells.
By Ron Wilson, Executive Editor -- EDN, September 27, 2007
Speaking at an IEEE-sponsored conference on the future of memory technology, Kazumi Ino, chief specialist in NAND technology at Toshiba, presented his views on the problems facing NAND-flash technology as scaling progresses toward 20 nm.
Although optimistic about the short-term viability of technology evolution, Ino believes that at some point a new storage mechanism will have to take over for conventional cells.
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Ino said that today, the industry is building 8-Gbit parts using 56-nm geometry. But moving to any geometry starting with a "4," he said, would probably require introduction of new materials into the process. He cited reduction in adjacent-cell interference as the most important task designers have to undertake.
The mechanism for this interference, according to Ino, is that during the programming sequence on a cell the immediate neighbor cells in both the bit-line and word-line directions are influenced just enough to alter their threshold voltages. This, in turn, can alter the contents of the cells, especially in multilevel storage devices.
Ino further pointed out that the shrinking size of the floating gate is causing other problems. It is becoming increasingly difficult for process engineers to fit all the necessary layers in the gap between adjacent floating gates. More mundanely, the gate is becoming so small that at the 40-something nm node, there will only be several hundred electrons stored on a fully charged floating gate. This means that to meet data-retention specifications, the gate can only lose about 10 electrons to all leakage mechanisms combined over the course of a decade. Ino was not optimistic about this.
Having laid out the problems, Ino reviewed currently promising solutions. One is to introduce ultra-high-k dielectric material for the interpoly dielectric. This makes it possible to move from today's stacked cell to a planar cell, which in turn reduces the electric field strength in the area of the floating gate, improving reliability. Other changes the industry is investigating, Ino said, involved finding a high-injection tunneling film, and moving from dielectric-film isolation to air-gap isolation between adjacent cells. These changes, Ino suggested, would keep the floating-gate cell viable through the 30-something-nm node.
Beyond that point, Ino said, the industry is investigating MONOS (metal-oxide-nitride-oxide-semiconductor) and SONOS (polysilicon-oxide-nitride-oxide-semicondcutor) structures, which store charge in traps within the gate oxide rather than on a floating gate. In principle such cells can be structurally much simpler than floating-gate cells. But charge is moved into the traps through direct tunneling, rather than the Fowler-Nordheim tunneling mechanism of floating-gate cells. This presents cell designers with an unfortunate dilemma: Direct tunneling is quite reversible, so in order to keep the charge in the traps, the oxide must be quite thick. That thickness slows the cell down dramatically. For this reason, and because changes in charge distribution within the traps can cause the threshold voltage of the transistor to shift, again losing data, Ino believes that the MONOS cell still requires a lot of development to be ready for prime time. But he clearly expects something without floating gates to take over at geometries below 30 nm.
