Mears Claims to Reduce Gate Leakage 60%-80%
By Ann Steffora Mutschler -- EDN, December 11, 2006
As circuit designs move to 65nm and smaller process geometries, the inverse power-to-performance ratio is becoming harder to sustain, driving the need for new material and process technologies to stay on the Moore’s Law curve, and Waltham, Mass.-based startup Mears Technologies Inc. is aiming to do just that.
Mears, which is being formally launched today, is focused on re-engineering the physical properties of silicon in order to reduce gate leakage by as much as 60 percent in NMOS transistors and up to 80 percent in PMOS transistors while maintaining drive current for deep sub-micron processes.
Through its work, the company aims to allow semiconductor companies to continue with aggressive device roadmaps while leveraging the semiconductor industry's existing manufacturing infrastructure, explained founder and president Robert Mears.
Given that silicon devices make up approximately 95 percent of the $250 billion semiconductor market and it is becoming increasingly clear that the limitations of bulk silicon are beginning to compromise the ability of CMOS manufacturing to deliver exponentially better performance at ever lower cost and power. Market research firm IC Insights reminds that while recently-introduced options offer a viable short-term boost in performance, the industry as a whole has been searching for a breakthrough that extends the life of CMOS and lowers power dissipation -- without requiring sweeping changes in materials or huge investments in new manufacturing equipment and facilities.
And since static power dissipation – also called gate leakage -- can account for as much as 70 percent of the total power budget of devices manufactured at the 65 nm process node, Mears is tackling the issues of chip performance and power consumption with its MST Platform.
The platform uses a band engineering approach to reduce gate leakage, and provide an advantage for all applications that benefit from reduced power consumption, along with enhancing drive current, which relates directly to increased semiconductor speed, Mears noted.
Explosive growth of the cell phone market along with other personal electronics devices has created conflicting demands for semiconductors with increased performance and reduced power consumption.
Mears explained that the ability of the industry to respond to these demands continues to depend on the electrical properties of a single material, namely silicon. As chipmakers attempt to squeeze more performance out of their transistors, the fundamental properties of silicon and its native oxide have become the limiting factor.
While some approaches have been successful in addressing performance requirements, power issues continue to exist.
Mears’ approach to silicon engineering alters the properties of the silicon to improve the power efficiency and speed of transistors manufactured using deep sub-micron process nodes such as 65nm, 45nm and smaller, while maintaining compatibility with standard CMOS manufacturing equipment that is used for the vast majority of today's semiconductors.
The MST Platform is meant to be compatible with semiconductor manufacturers' baseline processes, whether bulk CMOS, strained silicon or silicon-on-insulator.
Power improvements are achieved through a band engineering approach based on a deep understanding of the quantum mechanics of modern deep-submicron devices, Mears said.
The company’s management team includes Mears, who has more than 20 years of research experience in electronics and photonics and is the inventor of the erbium-doped fiber amplifier (EDFA), which helped enable the broadband Internet.
Scott Kreps is VP of engineering, previously with companies such as Harris Semiconductor (now Intersil) and Applied Micro Circuits Corp. (AMCC).
In addition, Dr. Marek Hytha, chief scientist, has more than 15 years of experience in condensed matter physics and is the successful developer of numerous ab initio quantum mechanical techniques for the calculation of chemical and solid state properties in materials.
The company is working with a number of partners including Sematech’s semiconductor R&D center, Advanced Technology Development Facility, epitaxial services provider Lawrence Semiconductor Research Laboratory, semiconductor analytical services supplier Evans Analytical Group, and Cornell Center for Materials Research, which is engaged in the study of materials purposefully structured at the nanoscale.
