How the SNRs of delta-sigma converters differ
This converter topology is a bit different from other topologies; however, many engineers still strive to fit this round peg of a converter into the standard ADC square hole.
By Bonnie Baker -- EDN, August 2, 2007
When I was a child, my parents bought me a 1-in.-diameter box turtle. I was so excited! To protect the turtle, I was going to put it in my block wagon. This wagon had slots to insert square, triangular, and round pegs. When my mom saw me grab a hammer, she knew it wouldn’t be a pretty picture. “You can’t fit a square peg—or a turtle—into a round hole,” she told me.
That lesson also applies to the basic concept underlying delta-sigma modulators and ADCs—a concept that has been around since the 1930s. This converter topology is a bit different from other topologies; however, many engineers still strive to fit this converter into the standard ADC square hole.
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Delta-sigma converters go beyond performing a simple analog-to-digital conversion. They have an oversampling mechanism, a modulator, and a digital filter. The oversampling mechanism spreads the noise power across a wider frequency range. The modulator shapes the low-frequency noise or pushes it out to higher frequencies. The digital filter averages the noise and eliminates it in the higher frequencies. The ideal successive-approximation-register and pipeline SNR (signal-to-noise ratio) is 6.02N+1.76 (Reference 1), where N is the number of converter bits. The delta-sigma-converter SNR is 6.02(N+NINC)+1.76, where N is the number of modulator bits and NINC, the increase in resolution, is:
In this formula, M is the order of the modulator, and K is the oversampling ratio during the conversion.
Ideally, the delta-sigma-converter SNR, with a first order modulator, is 6.02N+1.76–5.17+30log10OSR where OSR is the oversampling rate and N is the number of modulator bits—not converter bits (Figure 1).
These ideal formulas assume that the linearity, noise, and offset errors of the ADC and DAC—usually, 1-bit devices—are ideal and that the digital filter has an ideal brick-wall response. Actual delta-sigma converters are not as ideal as you would hope.
With these theories of the ideal, the best approach is still to rely on bench data for your converter performance. This data gives you a realistic view of the converter’s capabilities. On the bench, you can measure your converter’s rms noise by acquiring a few hundred samples of a dc-input signal. In this circumstance, the formula that describes any ADC SNR is 20log10(VRMS-FS/VRMS-NOISE).
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This little article was very helpful.
Many thanks from a student in Sevilla(España).
Pedro Nogueiro - 2010-3-2 07:47:00 PST -
I have read and enjoyed Bonnie Baker's writing for a long time, but I believe that this
article is unclear and misleading. In the formula 6.02 (N + Ninc) + 1.76, it should be
made more clear that "N" is the bits of the internal quantizer, NOT the converter output
number of bits. It would help greatly to use a symbol other than the "N" that is used in the
common 6.02N + 1.76 formula.
If (and only if) you really understand the delta sigma converter, you understand that this
article conveys the idea that the internal modulator has a very high SNR, but the SNR at
the entire device output is still limited by the same formula as is other converter
architectures. That is, it is still limited by the formula 6.02N + 1.76, where "N" is the
number of output bits.
The really nice thing about the delta sigma converter is the fact that you can get an SNR
very close to 6.02N + 1.76 at very high resolutions, where you can not get as close with
(most) other converter architectures at high resolutions. Perhaps this is what the article
was intended to say but does not say. It really seems to say that the THEORETICAL
BEST SNR of the delta sigma converter is higher than the SNR of other architectures.
Nicholas Gray - 2007-2-8 11:40:00 PDT
