IBM offers first high-k metal gate details
By Ed Sperling, Editor in Chief -- EDN, June 14, 2007
IBM opened its kimono for 45-nm technology today, detailing for the first time the high-k/metal gate technology it will be using to improve insulation and boost performance starting next year.
The paper, entitled “High-Performance High-k/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing,” is part of IBM’s future road map that will be integrated with Air Gap insulation around wires at future generations. It is being introduced at the 2007 Symposium on VLSI Technology in Kyoto, Japan.
Kirklen Henson, manager of IBM’s 45-nm High-k/Metal Device Group, said the big advantage of high-k is that it dramatically cuts current leakage and adds a 20 percent performance improvement. The performance, he said, comes from a boost in current at the smaller geometry.
IBM has said that classical scaling ended at 90-nm, but the high-k/metal gate technology restores at least some of that scaling. Henson noted that high-k/metal gates had been on the IBM road map, along with strain engineering and copper interconnects. He said Air Gap technology is the next step, which will appear at 32-nm, and that it will be complementary with the high-k insulation. Other new technology will begin appearing at 22-nm.
The paper lists authors from IBM, as well as Sony and Toshiba—two of IBM’s development partners for the 8-core cell processor used in the Sony Playstation 3—and AMD.
Gary Patton, VP of technology development at IBM’s Semiconductor Research and Development Center, said the high-k technology will appear in Power processors starting next year, with the rollout to follow at a later date in the Common Platform shared by IBM, Samsung, Chartered Semiconductor, Infineon and Freescale.
