Semicustom-IC technology

IC-design capability has finally entered the system designer's realm. As a result, you can create efficient single-chip implementations of complex circuits.

By Andy Rappaport, Associate Editor -- EDN, February 17, 1983

Get what you can and what you get hold,
'tis the stone that will turn your lead into gold.
—Ben Franklin

Semicustom-IC technology might represent the high-tech equivalent of Ben Franklin's proverbial Philosopher's Stone. Thanks to the convergence of rapidly improving silicon-fabrication, design-automation and chip-packaging technologies, you now can easily create fast-turnaround, inexpensive and well-characterized customized ICs without directly designing detailed geometric masks. And although the technique might not allow you to turn lead into gold, it does permit you to reduce system size, power consumption and cost while improving performance and marketability.

To properly exploit semicustom ICs' advantages, however, you must understand their capabilities and limitations, and you must structure your design projects in ways that anticipate—and simplify—silicon implementations of complex systems. For although semicustom-chip vendors promise to make IC design no more complicated than pc-board layout, the unique characteristics of silicon-level circuit implementations mandate several design steps that conventional standard approaches don't.

For example, successful semicustom-chip design depends heavily on proper circuit simulation, testability analysis and device characterizations. In addition, because semicustom-chip properties and capabilities vary widely, and because the chip-design process differs from vendor to vendor, profitable use of semicustom-IC technology requires a thorough awareness of available devices and knowledge of their manufacturers' approaches to device customization.

Meet the players

Semicustom ICs divide into two fundamental classes: array devices and standard-cell- or cell-library-based components. Many vendors also term PROMs and FPLAs semicustom chips, but according to United Technologies Microelectronics Center (UTMC) general manager Gordon Hoffman's definition of semicustom devices, such user-programmable components are really standard parts. Hoffmanmaintains that semicustom parts are ICs that look like standard units to component vendors but appear to be custom devices to users. PROMs and FPLAs, while customizable, require the same specification, purchasing and inventorying procedures as off-the-shelf, fixed function ICs. Array devices and standard-cell-based chips, on the other hand, allow vendors to employ many standard-component design and production procedures but require users to adopt customized development and handling methods.

The simplest semicustom-ICs—gate and component arrays—accommodate fast, relatively inexpensive design cycles and require minimal wafer customization. They consist of uncommitted-component matrices that allow user-defined interconnection through metal or (for some CMOS components) metal and polysilicon traces. Because the arrays employ fixed component locations and geometries, their manufacturers can fabricate wafers through several standardized diffusion steps and store those wafers for future customization. Thus, the devices benefit from large-volume production because they appear to be standard components through most process steps; vendors can offer them at relatively low prices and promise fast prototyping and production times.

Standard-cell-based devices, on the other hand, employ fully customized process-mask sets and therefore must be fabricated completely to users' specifications. To design such chips, users employ precharacterized function cells from vendor-supplied libraries, placing and interconnecting the cells in the same manner as they would place standard components on pc boards. The function libraries contain physical design data for all of the cells, so completed standard-cell designs constitute fully formed IC layouts. And because the chips include only cells that users require (rather than fixed numbers of components), standard-cell-based ICs provided efficient circuit implementations and typically require smaller—and thus less expensive—dice than array-based chips.

Unfortunately, because component locations and interconnection routing contribute to circuit performance, standard-cell-based designs require more thorough prefabrication simulation and design verification than do the more rigidly characterized array-based circuits. Moreover, unlike fixed-location component arrays designed with predetermined interconnection-routing channels, standard-cell libraries don't automatically prevent process-design-rule infractions. As a result, the systems on which they're designed entail greater complexities than do tools for array-IC design, and standard-cell development cycles remain longer and more costly than array-customization projects. In addition, standard-cell-based chips take more time to prototype and produce than do standard-diffusion array parts because each library-cell-based wafer must be fabricated from bare silicon.

Greater flexibility with standard cells

Design flexibility also distinguishes array devices from standard-cell-based chips. Gate arrays composed of matrices of digital gates excel in the performance of SSI- and MSI-equivalent logic functions, for example. Typically, the devices replace 74 Series TTL and 4000 Series CMOS logic components or perform functions similar to those of FPLAs. The silicon penalty that results from using such fixed-geometry component arrays, however, prohibits the economical implementation of LSI or memory functions in gate arrays. Moreover, although several array components offer linear capabilities, unless their analog portions are optimized for specific circuit types—such as switched-capacitor filters or data-acquisition functions—combined linear/digital arrays provide restricted analog capability.

Conversely, standard-cell libraries pose no restrictions on function complexity or circuit type. Cell libraries typically contain SSI and MSI digital functions, analog elements and memory arrays. In addition, American Microsystems Inc and Zymos Corp offer LSI microprocessor cores (µP-based library vendors plan to introduce similar LSI and µP-based library elements. Thus, the standard-cell approach to device customization allows the integration of a broader range of systems than those permitted by gate arrays.

Standard-cell-based designs also achieve greater I/O flexibility than do gate arrays. Digital arrays typically possess one I/O buffer for every 10 to 30 gates, a ratio designed to suit a majority of applications. Designs requiring significantly larger or smaller ratios, however, benefit from the standard-cell approach's I/O-customization capability. Input and output buffers are present in cell libraries along with logic and memory elements; you can therefore employ only the number of buffers and cell types (input, output, high-current, inverting, noninverting, etc) that your design require.

Despite their flexibility and more efficient silicon utilization, though, standard cells won't make gate arrays obsolete, as some cell-library vendors suggest. Standard-cell-based chips' higher development costs (typically $25,000 to $50,000 as opposed to gate arrays' $10,000 to $30,000) and longer design cycles make them inappropriate for small-volume production (typically less than 10,000 units/yr). And even as improved development systems and faster fabrication capabilities reduce standard-cell-based-chip costs, gate arrays will continue to cost less in small quantities. In addition, adding one or two customized layers to a standard wafer will always be faster than fabricating a completely new chip. And as silicon-fabrication costs continue to plummet, the need for efficient real-estate utilization in all but the most speed- or cost critical circuits will abate. Says UTMC's Hoffman, silicon already costs much less than the software and engineering talent needed to design it.

Silicon costs also pale in comparison with packaging expenses for high-pin-count circuits: As I/O complexity increases, device costs become package bound and designers find it increasingly difficult to justify the added development expenses needed to reduce die size. (Design efforts that reduce pin count, though, will always prove profitable, regardless of whether they entail the use of standard-cell or gate-array chips.)

Applications will drive technology

The relative successes of standard-cell and array components, furthermore, will be determined as much by the applications employing the devices as by the chips' capabilities. Currently, engineers pursuing semicustom-IC technologies are interested most in improving their products' speed, reducing costs in large production volumes or constructing very-high-density circuits. But as the technology begins to experience wider use in less critical applications—applications that benefit from semicustom ICs' assembly costs, minimal power consumption, high design security and small size—process speed, silicon efficiency and gate density will become less important for most designers. Instead, those designers will remain most concerned with minimizing design times and costs, implementing a broad range of functions on one chip and ensuring fast prototyping and production times.

The configuration of the semicustom-IC industry will also depend on progress in standard components. Many designers turn to customizable parts to eliminate the silicon redundancy entailed by standard-component use. Off-the-shelf devices almost always contain more clock, reset, preset and other circuitry than any particular design must employ, so systems built from multiple standard parts must include unnecessary redundant silicon. Intel Corp silicon-foundry manager Peter Jones explains, however, that as silicon price fall, so does the cost of such unneeded circuitry. If fivefold increase in device functionality requires only doubling of IC costs, standard components, even those with significantly greater capability than their host designs require, will remain economically viable.

In most applications, then, semicustom ICs will continue to replace the MSI and SSI components than surround LSI and VLSI devices. And as Texas Instruments gate-array marketing manager Tim Chambers points out, that's precisely the function that gate arrays perform best. The nature of standard TTL and CMOS-device functions suits their implementation via regularly situated identical gates and usually doesn't justify the development of standard-cell-base devices.

Chambers adds, though, that as more designers strive to implement greater percentages of their designs on single chips, standard-cell libraries will evolve from gate-array development systems. Unlike vendors that suggest the implementation of LSI and memory functions on dedicated portions of gate-array chips (Motorola, for example, plans a gate array with 1k bits of static RAM), he feels that design systems sufficiently complex to model LSI and memory functions will always be capable of manipulating mask data and will thus support standard-cell development. Furthermore, standard-cell approaches allow variable memory-to-gate ratios and eliminate the need for large numbers of standard dedicated-function/array wafers.

In anticipation of LSI-based cell-library development, TI has instilled its design system with some of the functions needed to develop standard-cell-based chips. The firm's recently introduced transportable design utility (TDU) supports its hardware- and test-description languages (HDL and TDL), which are capable of defining logic circuits and test patterns. The software runs on DEC VAX 11/780 and IBM 4341 computers as well as other processors that support Wirth-standard Pascal compilers. The software currently communicates with TI gate-array development programs through dial-up telephone links, but Chambers explains that the firm hopes to promote its development languages as industry standards for all types of circuit-design projects, including the creation of customized µPs and standard-cell-based chips. As a first step, TI has already modeled the logic of several of its µPs in HDL.

Cell library includes standard µPs

Recognizing the potential of µP-based standard-cell devices, Intel Corp also plans to make some of its widely used processors available as part of a standard-cell library. To simplify the creation of µPs with customized interfaces, such as those required for floppy-disk and printer control, the firm plans to introduce a library containing CMOS versions of 7400 Series TTL functions, data-conversion circuits and the stripped cores of 8048, 8049 and other standard single-chip µCs. By incorporating cells based on widely used, currently available processors, says foundry manager Jones, the library allows designers of semicustom chips to use existing emulation and software-development tools.

Even if they incorporate industry-standard cores, though, customized µPs still present software-design and –debugging difficulties. To ensure the emulation capability of user-configured processors, Jones predicts, designers will create chips that provide direct external access to all µP control, data and address lines. Such techniques, however, increase package pin counts and thus might negate the economic advantages inherent in single-chip customized-µP implementations. As a result, designers will have to ascend a new µP-development learning curve, discovering ways to more elegantly provide access to internal chip functions.

Similarly, as more complex circuits become embedded in semicustom chips, designers will have to address methods for ensuring their testability. Therefore, the inclusion of complex µPs in standard-cell libraries demands the development of sophisticated testability-enhancement techniques and chip-design software.

As cell libraries containing complex LSI and VLSI elements proliferate, it's likely that designers will use them to create hybrid gate-array/standard-cell ICs. Most design teams employ similar architectures in multiple products and systems, so each team could conceivably design a standard wafer incorporating those µP, memory and analog functions common to a range of systems and then add an array of uncommitted gates sufficient to customize the circuit for specific applications.

Thus, suggests UTMC's Hoffman, semiconductor vendors will produce semicustom-diffusion wafers with user-defined characteristics. Each company's wafers will undergo fabrication through all diffusion steps and then remain stored in bonded inventories, awaiting the deposition of customized metal layers. The aggregate volume of all applications for the diffusion masks will justify the development of the wafers' standard-cell-based components, but individual systems need only support the creation of array-based metal masks.

In preparation for hybrid standard-cell/gate-array wafers, UTMC has developed the basis for a library of cells that designers can integrate within existing gate arrays. The cells exhibit the same widths as the gate columns within the firm's CMOS arrays and thus can replace all or part of an array. In addition to providing functions that aren't feasible with only discrete gates and allowing the compaction of SSI and MSI logic functions, the standard-width cells permit interconnection routing using the automatic channel router that now completes gate-array designs. Thus, designers can create standard-cell-based devices using UTMC's currently available Highland design system.

To further enhance the efficiency and designability of standard-cell-based devices, UTMC has also developed a compaction program that shrinks array-routing channels to eliminate unused interconnection tracks. Using this program, designers can create ICs using standard array grids and then shrink the chips immediately before submitting design databases for mask generation. UTMC's standard-cell library will become available through Mostek Corp later this year; preliminary offerings will include memory functions.

Cell libraries must be extensive

UTMC's cell library probably won't be the only one that offers gate-array segments for chip customization. One of the advantages of array devices over standard-cell-based parts derives from gate matrices' ability to form any combinational or sequential circuits—provided that target designs can spare the silicon needed for the functions' implementations. Cell-library users, on the other hand, must use only functions contained in vendor-supplied libraries or create new elements themselves using physical-layout chip-design tools. Creating customized functions from numerous simple gates always remains a possibility, but the attendant layout, routing, simulation and database-management problems render such approaches difficult.

As a result, standard-cell vendors must design libraries that satisfy the largest number of applications with the smallest number of cells. In addition, each cell must offer enough I/O, clock and speed/power options to permit its use in a large number of circuits without creating the redundancy problems of individually packaged standard logic components. Designers who use standard-cell chip-design approaches to optimize silicon utilization won't tolerate unnecessary circuitry added to cells to enhance their universality.

These factors, says Zymos director of marketing Bill Loesch, help to explain why fewer companies offer cell libraries than produce gate arrays. A properly designed library must contain a large number of cells, and each cell must undergo extensive characterization. Thus, cell-library development entails significant time and expense. Conversely, once a gate array's basic components and interconnection traces have been characterized, new functions require only simulation before they're added to circuit libraries.

To circumvent some cell-creation problems, VLSI Technology Inc offers a cell-compiler library. Using a procedural language to define basic device structures, this library generates layout data for cells that exhibit user-defined performance. B y allowing designers to specify buffer drive current, number of bits in sequential-logic chains, preset sources, preset polarities, clock phases and similar performance data, a 20-element library can generate as many as 1200 discrete cells.

Even with such cell-customization capability, though, the firm expects most projects to require some manual cell design. Says applications manager Scott Nance, basic Boolean gates are simple to create using physical-layout tools and therefore don't justify the design of standard compilers. To support the custom generation of basic logic elements, the firm's design software provides both self-compacting symbolic editors and fully geometric layout editors.

Try gate arrays first

As cell-library vendors grapple with the problems attendant to diffusion-programmable chip design, gate arrays are providing a well-bounded technology that permits users and vendors to debug their semicustom-IC design capabilities without incurring significant risks. Many of the tools required for gate-array development—such as simulators, testability analysers and database-management software—also apply to standard-cell-based device designs, so by creating simpler devices first, users can acquire basic chip-design talents before progressing to more complicated development chores. Moreover, by introducing development products incrementally, deice vendors can ascend the semicustom-IC learning curve along with their customers.

To keep gate-array design as simple as possible, most vendors offer libraries of precharacterized functions similar to standard cells. Each library element defines the interconnection of multiple array components and thereby eliminates the need for gate-level circuit design. Array organization determines the characteristics of such function definitions and also affects overall circuit routability and gate-utilization efficiency.

For example, bipolar ECL gate arrays based on blocks of uncommitted transistors and resistors require library functions that define fixed metal patterns. ECL function definitions typically employ components located in one array blo9ck and include circuits as complex as flip flops and latches. Because each function employs a fixed interconnection geometry, vendors can accurately characterize—and guarantee—circuit behaviour. American Micro Circuits Corp, for instance, uses such hardwired function definitions to guarantee that its Q700 Series arrays meet the speed and power-dissipation specifications predicted by the firm's circuit-simulation software.

AMCC marketing manager Joe Conway warns, however, that designers who employ ECL arrays should remain aware of the parts' unique circuit-design characteristics. Although the arrays require more components to form sequential circuits such as flip flops than do TTL and CMOS arrays, ECL 's series-gated and wired-OR logic structures more efficiently form multiple-input combinational circuits. As a result, the number of ECL gates required to satisfy a specific application depends equally on circuit size and function. Furthermore, because ECL circuit design relies on the interconnection of discrete components rather than logic gates, designers typically can't create new library functions. Rather, designs must employ only those elements that exist in precharacterized libraries.

Flexible interconnection patterns

Other array types provide greater design flexibility. Because TTL and CMOS arrays employ discrete gates rather than uncommitted-component matrices, their definition of library functions remains more straightforward. Rather than comprising fixed interconnection patterns, TTL and CMOS function definitions merely describe the electrical connections needed to construct high-level logic functions. Precise interconnection patterns depend on the locations of available gates and routing channels and vary from chip to chip.

However, such flexible definitions result in variable interconnection lengths within logic functions, so the cells can't undergo complete prerouting characterizations. Therefore, designers must simulate their arrays after routing to assess the effects of interconnection capacitances and to predict device operating speeds. Flexible functions typically improve array utilization, though, because function-placement algorithms can bend and stretch library circuits to fit them into target arrays. However, to ensure adequate speed performance, layout routines based on flexible-interconnection libraries must allow users to define speed-critical paths and manually seed layout maps with functions that must reside in specific array locations.

Flexible-interconnection libraries also facilitate the creation and modification of function definitions. TI's STL (Schottky transistor logic) library uses HDL to define library functions in terms of discrete gates. The function definitions exist as subroutines that users embed in chip-design programs; to modify library elements, you need only edit function descriptions. TI's simulator flattens chip-design hierarchies, analysing all circuit activity at the basic gate level, so user-defined functions undergo the same performance characterizations as prestored circuits.

To enhance the versatility of its SCX 6360 6000-gate CMOS array, meanwhile, National Semiconductor Corp has developed what it terms stackable macros—functions that employ combined fixed and flexible interconnection definitions to provide customized multi-cell circuits. Here, complex functions such as shift registers and multiplexer consist of control and element macros; a single control circuit drives a user-definable number of element cells. Thus, users can create arbitrarily sized registers and counters without risking the silicon waste typically associated with interconnecting multiple fixed-width cells. In addition, the firm has designed the cells for adjacent placement within gate matrices, so multibit structures use silicon real estate efficiently.

Unfortunately, explains marketing manager Dennis Sabo, the stackable macros provide so many degrees of placement and routing freedom that currently available automatic-layout programs can't handle the cells. Thus, National is developing a set of algorithms intended specifically for stackable-macro layout.

Besides providing unique functional overlays, theSCX6360 also incorporates an internal signature generator for enhanced testability. The array employs 3-µm design rules and features gate delays of 2 nsec typ and maximum flip-flop toggle frequencies of 66 MHz.

Designers prefer CMOS

The 6000-gate SCX6360 is typical of the types of devices being implemented in CMOS. And as more manufacturers enter the gate-array marketplace, silicon-gate CMOS is clearly emerging as the preferred process technology. Advances in fine-line lithography allow the production of multikilobit arrays with reasonable die sizes, and small gate geometries result in operating speeds rivaling those of older bipolar devices. Indeed, of the 45 US-based firms currently offering digital gate arrays, two offer CMOS parts for every one that offers a bipolar component.

Perhaps CMOS's most appealing feature is its inherently low power consumption. Bipolar gates, which typically dissipate 2 to 5 mW each, don't suit use in very large arrays. Because packaging and cooling technologies limit practical array dissipation to a few watts, bipolar-array densities must remain at the 1000- to 2000-gate level. And although I²L gates dissipate less power than TTL and ECL gates, their operating speeds don't compare with those of still-lower-power CMOS devices.

Moreover, CMOS gates prove easy to design with and characterize. The process's complementary transistors provide symmetrical, short rise and fall times, and the bi-directional transmission gates that CMOS devices easily form simplify the construction of sequential logic circuits. Process refinements also render some CMOS arrays less expensive to fabricate than their bipolar counterparts.

A few CMOS arrays even possess speed characteristics compatible with those of power-hungry ECL devices. For example, National's 2-µm SCX6212 and SCX6224 silicon-gate CMOS arrays furnish internal gate delays of 0.5 to 1 nsec. Similarly, Fairchild's 2µm, 4000-gate GC4000 features 1-nsec typ gate delays and operates at external data rates to 50 MHz. And Universal Semiconductor Inc's 3-µm ISO3 Series arrays operate with 0.9-nsec typ gate delays. Moreover, CMOS gate arrays are likely to benefit from process improvements stemming from the US Army's VHSIC (very-high-speed integrated circuit) program; CMOS VHSIC chips are predicted to possess gate delays of less than 1 nsec.

The same process refinements that produce high-density, subnanosecond CMOS arrays, furthermore, render more common 5- to 8-µm-geometry parts inexpensive and reliable. Although most applications don't require gate delays of less than 5 to 10 nsec or capacities of more than 1000 gates, improvements in high-end parts benefit all CMOS-array users. Explains California Devices Inc president Bob Lipp, conservative fabrication processes create reproducible, easily second-sourced components; as more fabrication facilities gain experience with 2- and 3-µm arrays, larger geometry parts pose few manufacturing difficulties.

Analog arrays come in CMOS , too

CMOS processing technologies also permit the fabrication of single-chip analog/digital circuits. Telmos Inc, for example, uses an oxide-isolated CMOS process in its TM6000 Series arrays. The silicon-gate components feature as many as 450 uncommitted gates and 48 flip flops fabricated using 4-µm design rules; they provide as many as 750 uncommitted 6-, 12- and 24-µm-gate FETs for analog functions. The process allows the construction of op amps with 5-MHz unity-gain bandwidths and permits TM6000 chips to contain as many as 180 1.5-pF MOS capacitors.

Because of their on-chip capacitors, CMOS linear/digital arrays suit use in specialized linear circuits. For example, several manufacturers have introduced arrays optimized for customized switched-caacitor filter circuits, and as filter requirements in communication and signal-processing systems become more stringent, it's likely that such devices will find widespread use.

Technology fallout

As semicustom-IC technology continues to produce components with higher density, faster speeds, higher pin counts and greater versatility, it will also determine the futures of several allied technologies. For instance, the need for tools that support the design of complex integrated systems has already spawned a new industry: CAE workstations capable of performing most phases of system, circuit and IC design have grown from concept to finished product in only the last 2 or 3 yrs (see box, "Supporting semicustom-chip development"). In addition, as designers begin to integrate circuits requiring more than 64 I/O lines, leadless chip carriers and pin-grid arrays will become more prevalent, and packaging designers will be forced to hasten the development of lower-cost, higher-pin-count IC enclosures.

More important, effective chip testing is emerging as the foremost obstacle to successful semicustom-IC design. Unlike pc boards, which allow probing and modification, ICs permit circuit observation and control only from external I/O pins and can't undergo design changes without total refabrication. As a result, system designers must learn to instill their circuits with sufficient logic and I/O capability to allow comprehensive testing, and they must begin to simulate designs to verify logic function and ac behavior before chip fabrication.

Moreover, because each semicustom IC requires a unique production-test program, device vendors must continue to develop tools for rapid test-vector generation and test-programming formatting. Tester manufacturers, too, must assist designers by producing instruments that permit fast test-program development and rapid, comprehensive device analysis.

Semicustom-IC evolution will also affect the custom-chip industry. Custom-IC vendors have used standard-cell technology internally for some time, so user-accessible cell libraries represent a natural extension of traditional custom-IC procedures. Several custom-chip vendors—including American Microsystems Inc, Synertek and Silicon Systems Inc—have already announced such user-operated design systems, and others are likely to follow suit. Therefore, as more system designers become proficient at chip layout, and as standard-cell libraries become more comprehensive, custom-IC designers will be relegated to cell-creation and process-characterization functions.

Moreover, improving silicon-compiler technology threatens to further reduce the need for full-custom, hand-drawn IC design cycles. VLSI Technology's cell-compiler library represents a first step toward practical computer-generated mask design and demonstrates the feasibility of the technology. In addition, automatic PLA generators have aided in the design of at least one commercially available IC—Seeq Technology Inc's single-chip Ethernet controller. Such an array-logic generator is available now as a part of Metheus Corp's CAE-workstation software, and a similar program if forthcoming from Silicon Compilers Inc (San Francisco, CA)>

Field-programmable logic arrays, too, will play a greater role in system design as more engineers turn to semicustom ICs. The devices provide prototyping capabilities not available with gate arrays and standard-cell devices and thus fill an important niche in the component-customization hierarchy. For instance, FPLAs will simplify semicustom-IC final-step programming and pin-count reduction by adding application-specific logic to chips designed for multiple systems. Moreover, designers can add FPLA circuits to standard-cell libraries (several libraries already contain PROMs) and thus facilitate the creation of chips programmable on two levels.

As a first step toward merging FPLA and gate-array technologies, Semi Processes Inc offers CMOS gate arrays configured to emulate 16- and 20-pin bipolar PALs. The devices let designers prototype circuits using power-hungry fuse-programmable parts and then convert the designs to low-power CMOS for volume production. Says marketing manager Don Hargrave, the gate arrays don'e precisely mimic PAL architectures, so delays depend on circuit specifics and I/O requirements; the so-called C-HALs typically exhibit 35-nsec total propagation delays. Because they derive from designs known to fit into small programmable arrays, the C-HALs require minimal engineering effort. SPI accepts logic descriptions in Bolean-equation or truth-table form and charges no engineering fee for orders larger than 5000 pieces.

References

1. Allen, C, "Some Thoughts on Very Low-Cost Integration (VLCI)," Session 10, Wescon, September 1982.

2. Huffman, G, "gate-Array Logic," EDN, September 30, 1981, pg 86.

3. Kroeger, J, "Gate Arrays: Low Risk Access to Integrated Logic Technology," Session 10, Wescon, September 1982.

4. Loesch, W, "Custom ICs from standard cells: a design approach," Computer Design, May 1982, pg 227.

5. Pate, R, and Berg, B, "Observe simple design rules when customizing gate arrays," EDN, November 10, 1982, pg 113.

6. Rappaport, A, "Instruments (Product Showcase)," EDN, July 16, 1982, pg 106.

7. Rappaport, A, "Automated design and simulation aids speed semicustom-IC development," EDN, August 4, 1982, pg 35.

8. Rappaport, A, "Programmable logic arrays fill the standard-component/gate-array gap," EDN, January 6, 1981, pg 59.

9. Source III Inc, Gate Arrays: Implementing LSI Technology, Electronic Trend Publications, Cupertino, CA, 1982.

10. Twaddell, W, "Uncommitted IC logic," EDN, April 5, 1980, pg 89.

11. Twaddell, W, "Semicustom-logic suppliers differ on how to best deal with testability," EDN, November 24, 1982, pg 69.

Supporting semicustom-chip development Semicustom-IC design relies heavily on computer-aided tools. Mot chip vendors offer automated data-entry and simulation aids, and several offer user-operated automated layout systems—available either through timesharing links or for operation on local minicomputers. But vendor-supplied tools typically assist only in the design of the manufacturer's components. Moreover, automated-design systems offered by IC manufacturers usually provide only alphanumeric data-input and –output formats and thus force users to learn complex coding and data-interpretation schemes. More important, though, IC-vendor-supplied design systems typically don't integrate well into overall system-development projects. The programs excel at silicon-level design chores but rarely allow engineers to assess the effects of newly developed devices on overall circuit performance. Furthermore, designers creating complex systems that employ multiple device types frequently must learn several design techniques and operate numerous disparate development systems. What's needed, therefore, is a unified system-development tool that lets designers start projects by defining overall system behavior and then hierarchically develop functional and circuit blocks. Beginning with system-level design and analysis, designers could gradually add detail to circuit descriptions, ultimately branching into device-specific development cycles. The same system could, in theory, aid in the design of standard-component-based circuit blocks, PLAs, gate arrays, standard-cell-based ICs, µP-based functional elements and full-custom chips. And to maintain design-cycle consistency, such an ideal system-development tool would allow analyses of component interactions, permitting system-cost, -performance and –development-time optimizations. Furthermore, by supporting generic design tasks, the system would defer specific semicustom-device and –vendor selection until final project stages. Although such totally integrated system-design tools remain a few years away, several CAE-workstation vendors have taken the first steps toward providing instruments that support chip- as well as system-design functions. The workstations accept design data in schematic form and guide development programs through definition, simulation, device-specific circuit design, design verification and project documentation. One such workstation, Metheus Corp's (Hillsboro, OR) ë750, provides system-design functions as well as color-CAD capabilities optimized for IC layout. The $75,000 unit supports schematic capture, logic simulation, gate-array routing, standard-cell libraries, design-rule checking and automatic extraction of electrical characteristics from physical-layout databases. In addition, the system's color layout editor aids in the generation of new library cells or the customization of existing ones; an automatic PLA generator—a primitive silicon compiler—further eases system-to-chip design transitions by converting Boolean expressions directly to fully formed IC-mask designs. The ë750 includes a proprietary 68000-µP-based processor that runs under both UNIX and a specially developed real-time I/O- and graphics-control operating system. The desk-housed workstation supports user-definable process design rules and communicates to back-end wafer-fabrication services through Caltech Intermediate format (CIF) database transfers. A similar system, VLSI Technology Inc's design-software package emphasizes physical IC layout as an integral part of system design. This system features both symbolic and fully geometric layout editors that facilitate the creation of basic circuit elements. A procedural chip-design language, VIP, allows structured cell-interconnection descriptions; network-extraction and switch-level simulation programs ease layout-database/system-definition comparisons. To support system-level design tasks, VLSI Technology plans schematic-capture, logic-simulation and block-level-project-planning software. The $160,000 multiuser design package runs on DEC VAX minicomputers; a $122,000 single-user turnkey system includes an Apollo Computers Inc domain engineering workstation. Optimized specifically for gate-array development, Daisy Systems Corp's (Sunnyvale, CA) Gatemaster package lets users design logic first and then settle on specific target arrays. The software, which runs on the color version of Daisy's Logician workstation, links with schematic-entry and simulation programs to promote integrated device development. According to product marketing manager Randy King, users can begin design projects by defining circuits either in trms of 7400 Series TTL components or functions that correspond to an IC vendor's precharacterized cell library. A modeling program allows mapping of schematic functions to arbitrarily defined circuit cells, so users can select one library for design and another for chip layout. As a result, the system lets users try circuit layouts on several target arrays in order to select the one that works best. Because Daisy's modeling program queries design databases, users can define intelligent function models. For example, the modeler can check designs to see if flip-flop occurrences require preset and clear signals and select the library element that provides the minimum required circuit implementation. Similarly, the modeler can stack multiple elements to form arbitrarily sized counters and registers. To create completed array layouts, users convert generic design databases to array-specific formats, using array-support files. Each file contains library-conversion data, basic array-structure information, electrical and physical design rules and an output formatter compatible with the array vendor's mask-generation equipment. The Gatemaster program supports function placement and interconnection routing through several layout programs. A manual placement routine lets designers seed automatic placement algorithms with speed-critical functions and fixed-location pin designations. Then, a relaxation-based automatic-placement program completes function overlays by grouping components together based on the number of interconnections, or forces, that bind them. King likens the process to the settling of a matrix of marbles connected by rubber bands of various sizes; the assembly finds a point that minimizes the forces on each internodal connection. Gatemaster's global channel router and local maze router plot interconnection patterns automatically, typically completing layouts for 90%-utilized arrays. A manual layout editor allows interactive routing of interconnections not automatically generated; continuity-checking routines driven by both schematic and layout data prevent invalid layout operations. King claims that the $115,000 system (color hardware and software) handles arrays as large as 10,000 gates; the layout programs typically place functions on a 1000-gate Motorola ECL Macrocell array in 15 to 20 min and route all interconnection traces in less than 30 min. Daisy currently supports Motorola and Applied Micro Circuits arrays; support for National Semiconductor components will be available shortly. The firm plans to offer support files free, on the ongoing basis, to users with maintenance agreements. Mentor Graphics Corp (Portland, OR) also supports gate-array development on its IDEA Series workstations. Employing software licensed from California Automated Design Inc (Santa Clara, CA), the systems aid in automatic function placement, automatic interconnection routing and manual layout editing. The system is technology independent and accepts array data in Calma stream format. Mentor is working with several foundries to acquire function libraries, design rules and array specifics in the workstation's format and to create output-generation programs that speed database interchanges between designers and chip vendors. According to Mentor vice president for marketing Gerry Langeler, the gate-array development system's power lies in its ability to efficiently route dense circuits and to provide growth paths that ensure the ability to support increasing design complexity. Workstation-based programs route chips containing 2000 to 3000 gates and allow uploading of larger design files to host-based layout routines. For simplified operation, the CADI layout program operate with the IDEA workstations' graphics kernel, providing multiple display windows for simultaneous viewing of several chip sections. Because gate-array layout usually requires manual editing, Langeler predicts that most designers will use the $100,000 routing software on the $100,000 color version of the Apollo-Domain-based IDEA 1000 workstation. But for applications involving less than fully utilized arrays, the smaller IDEA 1200 workstation might prove appropriate. Based on Apollo's desktop processor, this $50,000 system provides all of the IDEA 1000's schematic-entry and simulation features but provides only a monochrome display. Offering a semicustom-IC design package that runs on a variety of hardware, Silvar-Lisco Corp (Palo Alto, CA) provides programs for schematic entry, simulation, gate-array routing and standard-cell placement and routing. The software runs on DEC, Prime, IBM and Apollo computers, and a database manager links the discrete elements to form an integrated design system. The firm's IC-design programs comprise GARDS (for single- and 2-layer gate-array design) and CAL-MP (for standard-cell assembly). In addition, the firm currently offers DIANA, a digital/analog simulator especially well suited to the analysis of switched-capacitor-filer networks. And it plans to introduce a high-performance logic simulator with extensive circuit-modeling capabilities later this year. Silvar-Lisco's software is also available through the Cybernet timesharing network supported by Control Data Corp's Information Systems Design Group (Santa Clara, CA). In addition to Silvar Lisco's programs, Cybernet users can gain access to a range of chip-design and –verification tools, including TEGAS and LOGIS logic simulators, ASPEC and SYSCAP circuit simulators, the GEMINI-MOS device simulator, several semiconductor-process-analysis tools and NCA Corp's electrical- and design-rule checkers, network extractors and mask-generation software. CDC offers Daisy Logician workstations as front-end data-entry tools, but you can use the programs from any remote terminal. Taking a different approach to semicustom-IC design, Via Systems Corp (Billerica, MA) emphasizes the economy inherent in manual layout of small gate arrays. Through a licensing agreement with Master Logic, it offers software for its Model 130 CAD system, which supports function placement and interconnection routing of 50- to 400-gate CMOS arrays. Users place predefined cells onto array grids, using graphics overlays, and then route the matrix using an interactive wiring program with an on-line design-rule checker. Via converts completed databases to pattern-generator formats compatible with Master Logic fabrication processes. Users can order customized devices from Master Logic or purchase stock wafers and secure independent customization services. The GATES (Gate Array Technology Engineering Support) package costs $25,000; CAD hardware costs $90,000. Via plans to introduce schematic-capture and simulation programs.

 

Maintaining a competitive edge One of the principal advantages of semicustom ICs is their ability to enhance product marketability. By shrinking system size and cost and by instilling fixed-cost and fixed-size products with greater functional capabilities, the devices often provide their users with a significant competitive edge. Thus, the first product in any market that employs well-conceived and –designed semicustom chips will almost certainly direct the designs of its competition. For example, consider the Timex/Sinclar Z1000 personal computer. Thanks to a Ferranti bipolar gate array that contains most of the processor's control and interface logic, it was the first computer to break the $100 price barrier. Rivals must now employ custom or semicustom devices to be able to offer similar performance and value. Industrial products also benefit competitively from semicustom-chip utilization. Micro Networks Co (Worcester, MA), for instance, employs a California Devices Inc HC3100 300-gate array in its MN574A hybrid 138-bit ADC. Explains strategic planning manager Chuck Sabolis, the ADC—a second source for Analog Devices Inc's (Norwood, MA) AD574—would have been too expensive to produce without the semicustom chip. Analog Devices's part employs full-custom devices fabricated in that firm's captive IC facilities and thus allows competitive second sourcing only by companies with IC-design capabilities. Semicustom-IC technology offers that capability to companies not actively involved in chip production. Sabolis claims that his firm's design utilized 90% of the CDI chip and contains all of the ADC's successive-approximation, clock, timing and control circuitry. The 3-chip hybrid consumes significantly less power and undergoes less expensive assembly than comparable 5-chip circuits and thus competes effectively with the 2-chip ADI part. Furthermore, the gate-array design approach resulted in less hybrid-development time and expense than required with a full-custom circuit implementation, despite the three chip-design iterations needed to optimize speed-critical paths.

 

Getting involved As enticing as semicustom-IC technology appears, exploiting it requires significant care and forethought. You must ensure that device-development procedures become well integrated into overall system development, and you must weigh the risks entailed when undertaking a new design approach against the benefits offered by semicustom-chip technologies. The following recommendations summarize some of the factors to consider when getting involved with the technology and provide a starting point for chip-development programs. Get involved in the technology now. Virtually every design that's in volume production can benefit from the use of semicustom ICs; you should begin to analyze how you can best apply semicustom devices in your designs and whether you can justify the costs of developing and maintaining semicustom chips. Remember, even if you don't keep pace with the technology, your competitors will. Proceed with caution. Getting involved in the technology doesn't necessarily mean immediately embracing the state of the art. Carefully determine which approach—gate array, standard cell, programmable logic, etc—best suits your needs and begin with your least complicated application. Most semicustom-chip design processes entail considerations with which you're likely not to be familiar, so its' best to learn by defining a relatively simple component. Furthermore, before committing to a vendor, learn as much as you can about all the alternatives. Most vendors offer training courses and design manuals that can help you to determine the design approach that best suits your product-development cycles. Decide who should design your ICs. If you intend to create only one or two semicustom devices, you should probably let an experienced designer develop the devices. Vendors that offer complete design services typically charge less for simulation, layout, test generation and testability analysis than it would cost you to develop the necessary skills and design a single chip yourself. Moreover, if a vendor designs a chip for you, it's solely responsible for producing functional, testable chips (provided your original logic diagram is correct). If you intend to develop many devices, on the other hand, you should try to develop chip-design skills yourself. Development costs drop sharply as you ascend the semicustom-IC learning curve, and by developing your own devices, you can closely control design cycle time and avoid development delays. In addition, in-house designs usually don't require the release of proprietary schematics and other circuit data to outside vendors. And most important, you always understand your system better than outside designers do, so by controlling chip layout and test generation you can ensure a semicustom chip's compatibility with its companion devices in a design. Try to create devices that satisfy more than one application. Frequently, different products require ICs that differ by only a few gates or I/O lines. You can design chips—especially gate arrays—that contain the needed circuitry for many systems and customize them either through pin programming at the board level or through selective wire bonding during packaging. Furthermore, if your designs don't allow extra gates for multiple applications, you might still be able to use design similarity to reduce development cost: First design a mask set that embodies all of the circuitry common to multiple circuits, then use that design as the starting point for multiple, customized chips. Keep your designs small. Current IC technology permits implementation of more than 5000 gates in a semicustom chip, but because design production and testing costs rise nonlinearly with increased die size, such large devices often cost more than several smaller chips. Furthermore, large devices cost more to alter than do small chips, so if you anticipate changes in your design, try to include the circuitry that's likely to change in one limited-complexity device. Remember also that I/O requirements depend on chip complexity, so dense devices require packages capable of supporting a large number of pins. Because high-pin-count packages entail high purchase and assembly costs and are often less reliable than smaller enclosures, you might profit by partitioning your circuits into multiple limited-pin-count sections. Make certain that your designs are testable. You can't place ICs on bed-of-nails test fixtures, and you can't cut and patch a chip's interconnection traces to isolate faults. As a result, you must rely on simulation and fault grading to determine that all chip states remain testable. In addition, become familiar with techniques for testability enchancement (such as LSSD testing and circuit partitioning) and include circuitry to support those methods in your logic designs.