Midrange device includes SERDES function
By Michael Santarini, Senior Editor -- EDN, September 19, 2006
Lattice Semiconductor has announced a midcapacity, midpriced FPGA that includes some of the high-speed, high-end functions you typically only find in the most advanced and priciest Xilinx Virtex and Altera Stratix FPGAs. The company's new ECP2M FPGA family adds high-speed embedded SERDES (serializer/deserializer) I/O plus a pre-engineered PCS (physical-coding-sublayer) block to the company's midrange-FPGA lineup.
Shakeel Peera, director of strategic marketing for high-performance FPGA products at Lattice, says that, over the last few years, the high-end telecommunications and storage markets have been demanding SERDES blocks. FPGA vendors responded by offering these blocks in their high-end FPGAs. "Demand for SERDES has expanded beyond telecom and storage markets," says Peera. "The industrial, automotive, broadband-access, and consumer-electronics markets are also interested in FPGA technology. High performance is now the domain of not only the low-volume, high-end FPGA market, but also the high-volume, medium-density market." However, Xilinx's and Altera's low-cost, high-volume FPGAs, Spartan and Cyclone, respectively, lack SERDES functions. "The big guys haven't put these functions into their midrange devices because they are worried about cannibalizing their high-end devices," says Peera.
Now, with the ECP2M FPGA family, Lattice offers four to 16 channels of 3.125-Gbps SERDES in a quad-based architecture ranging from one quad to four quads with each quad including four SERDES channels. The device also includes PCS with 8b/10b encoding, an Ethernet-link-state machine, and rate-matching circuitry. This SERDES/PCS combination suits the device for PCI Express; Gigabit Ethernet; Serial RapidIO; and wireless-interface standards, such as OBSAI and CPRI. "Because we added the high-speed I/O, we also increased the on-chip RAM by five to six times over the previous parts in the ECP2 family," says Peera.
The new LatticeECP2M family includes five devices ranging in density from 20,000 to 95,000 look-up tables. The devices will feature 24 to 168, 18×18-bit multipliers two DLLs (delay-locked loops), and eight PLLs (phase-locked loops) for timing control. Lattice offers the devices in fine-pitch BGA packages with 144 to 601 I/O pins. The devices operate from 1.2V power supplies. Lattice's first product in the family, the ECP2M-35, costs $22.95 (100,000) and will be available in 2007. Stan Kopec, vice president of marketing, claims that the price is roughly one-third of the competition and that the part will address approximately 80% of SERDES applications.
