Thanks for pointing out that Q2 (and Q1) have swapped G1/G2. I had not noticed those errors. Also, refer to the previous comments to note the other numerous errors in the publcation.

Q2 is necessary in order to minimize the loading on the oscillator circuit and to provide enough drive for Q3. Minimizing the load on the oscillator circuit increases its stability.

Q3 is necessary in order to provide enough drive to allow the use of a 50 ohm load, if desired.

Dear Sir, I don't understand why there are three stages.
The Q2 has swapped G1/G2, the output signal cleanup is provided by Q3. Two transistors are requred.
If you want to make an oscillator, make the Vackar with FET.

Further comments on my oscillator circuit:

I was designing a Hartley Oscillator and I wanted to use SPICE to verify and optimize the circuit before I built the circuit. I realized that with my limited test equipment, I would have a difficult time getting an accurate value for the coupling coefficient, k. I remembered that the coupled inductors could be replaced by an equivalent circuit which contained no coupled inductors, so then I thought it would be interesting to design and build the oscillator utilizing the equivalent circuit. (which I did.)

Also, it provides a way to specify k and then check the circuit out with SPICE. Then if the normal Hartley oscillator is desired, just adjust the coupling of the inductors to make the circuit mimic the operaton of the simulated circuit with no coupled inductors.

This was not an attempt to create the "best" oscillator circuit. I found it to be an interesting circuit, and I thought it might be interesting to others.

Dear Sir,

I do not understand the utility of an Hartley oscillator in such an application. Doing a jonction at, I'll said 1/3 is a difficult task without any interest. Instead of that, a bridge with two capacitors is a better way or much better, a Clapp or Vackard oscillator. Because Frenchman's like complicated thinks, we said : why doing thinks simple when it is possible to do it complicated ...

Thanks to the editor's re-writing of my Design Idea to make it more reader-friendly, it contains several errors and much muddled text.

First, the problems with the figures:
In Figure 1b and 1c, the core symbols should be removed; LB and LC are not coupled. The core symbol in Figure 1a is optional.
In Figure 2, Diode D3 is inverted: the cathode should be grounded. Also the value for C17 is 200 pF, not 240 pF.

Now to problems with the text. Paragraph numbers:
1) k is difficult to determine and therefore the circuit is difficult to accurately model. This isn't clearly stated. The circuit is often built without knowing k with much accuracy. This is ok if you don't want to do a software simulation before finalizing your circuit.
2)The equations were obviously deleted from Fig. 1, and were inserted in the text instead.
6) Since the capacitive divider (C6, C7, & C8) presents only 6 pF across the tank circuit, the remaining 60 pF can be a variable capacitor, if desired. This is muddled in the text.
7) L2 is a low-Q choke with high losses at 18 MHz. The dc resistance should be < 2 ohms. A standard-value choke can be used if it meets these requirements.
The properties for L1 are less critical, but it should have a low Q (about 4 - 6) and low dc resistance (about 5 ohms or less).
8) The potentiometer is R15, not R5.
For a fixed-frequency oscillator, the output circuit's loaded Q of about 4 provides adaquate bandwidth so that the output circuit does not require tuning. This is extremely muddled in the text.

Finally, some variation of the word "comprise" is used at least 8 times. I think this is unnecessary and annoying. My original text had zero instances of this overused word. But, oh, well that is just my subjective opinion.

My original submitted material was both clear and accurate. And probably quite readable by any engineer.

If you need more clarification for this Design Idea, please post a comment. It was interesting and fun to design and optimize.