Sigma-C and Mentor make strides in DFM
By Michael Santarini, Senior Editor -- EDN, March 16, 2006
Announcements from Sigma-C and Mentor Graphics bode well for IC-design groups wanting to spot and fix lithography hot spots in their IC layouts before they send their designs to the mask shop. Sigma-C has announced the Solid+ microlithography simulator for design and OPC (optical-proximity correction).
Meanwhile, Mentor Graphics' Calibre group has introduced a tool for mask makers. However, the company says that the product's underlying pixel-based simulation engine sets the stage for a bigger release, this year, of a design-centric microlithography simulator. The microlithography-simulation niche of the DFM (design-for-manufacturing) market is becoming important as process geometries shrink below 90 nm, driving mask costs into the millions of dollars. Masks on these processes require OPC on all layers and thus take more effort and cost.
With Solid+, engineers use full-chip, third-party lithography simulators to locate trouble spots and then use Solid+ to do detailed 3-D analysis, says Peter Feist, chief executive officer of Sigma-C. Users feed Solid+ a GDSII file, and, after simulation, the tool generates a resist profile. Engineers can then overlay their desired layout and the simulated print showing how it would appear in the photo resist, thus exposing areas in which violations are likely to occur. The company has thus far identified three usage models for the tool.
First, IC and custom-cell designers can use the tool to perform resist-level simulation of layout and cells larger than 20×20 microns to let designers know whether the photo resist can accurately produce their patterns at smaller process nodes. Second, engineers can use the tool for developing OPC rules decks. Mask problems often occur because OPC rules are not well-defined; vendors build them using results from less-accurate 2-D simulators. Designers can use Solid+ to ensure the accuracy of OPC rules decks.
Mentor Graphics' OPC verification tool, OPCverify, mainly targets mask makers and qualifiers who want to check pattern fidelity before committing to a mask. The tool takes in the drawn layer, an OPC-corrected layer, and a run file and then uses a new pixel-based engine to simulate a silicon image as it would show up on the output of a scanner. The tool then gives a contour of every shape on the chip.
OPC engineers can also use the tool to ensure OPC rules are robust on many designs. OPCverify sets the stage for an upcoming release targeting IC designers. Lithographic simulation will become commonplace, but, to make it effective, designs have to take OPC into account—essentially imitating everything a fab facility does. "As we get to 65 and 45 nm, pattern fidelity is a huge issue," says Charlie Albertalli, product manager for Mentor. "It is getting harder and harder with low-k processes to absolutely replicate a design shape. Certain topologies look good at nominal dosage and focus, but, as soon as you remove the OPC, the image rapidly falls apart."
