COS-MOS Could Put Computer Slice on a Chip
By Staff -- EDN, April 1, 1970
EDN asked Allan Alaspa what it would take to build a complete computer of these powerful chips.
"I and another engineer have been playing around with that very idea on our lunch hour," he said. (RCA's contract with NASA has been completed and NASA has what it needs for its onboard data reducers for scientific satellite experiments).
"We have taken a PDP-8 computer as a proposed goal. We estimate that it would take 12 of the 4-bit processors to make up the basic four registers, each with 12-bit words. Then we would want to add a couple of dozen ROMs (read only memories) to carry some 100 instructions, and then a half-dozen RAMs (random access memories) and four buffer arrays to hold the data in transit between the processors and memories and input-outputs. We would, of course, put the ROMs and RAMs on similar-sized LSI chips as we expect their integration to be much less of a problem than that of the processor chip.
"All in all, we think between 50 and 100 chips of this LSI level might be needed to construct a medium-sized computer with PDP-8 capabilities. Of course, fewer chips would be needed for minicomputers and desk calculators, but our present processor chip really has more computing power than is needed for these smaller machines."
Cost of this imagined LSI PDP-8 would be the same or better than that of the present PDP-8, Alaspa is convinced. With sales volume, the LSI version ought to cost significantly less. The LSI silicon devices initially would add up to more, but there would be considerable savings in packaging hardware such as PC boards, connectors, back-plane wiring and cabinetry. Dingwall estimated that you could put everything on a 1-ft2 PC board, or better yet, you could chip and wire bond it on a single large ceramic hybrid substrate.
The power supply should be much less expensive because low-power COS-MOS needs only a watt or two. It could even run on batteries as it does in NASA's satellites.
A COS-MOS PDP-8 would be much slower than the present product. The chip described ran at only 250 to 500 kHz. However, if chips were constructed on sapphire substrate, which would lower gate capacitance that ordinarily loads down COS-MOS circuits, the speeds of well over 1 MHz should be possible. (Another RCA paper at ISSCC described a silicon-on-sapphire (SOS) COS-MOS shift register that can run at over 75 MHz!) SOS is still new and exotic so that it probably will be expensive for the present, but it has the exceedingly attractive feature for LSI of also improving the speed-power product of COS-MOS. Someday it ought to permit very fast chips that still run reasonable temperatures.
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COS-MOS Proves It
He refers particularly to the extensive use of bidirectional COS-MOS transmission gates. With these two-way gates, a single line serves as both input and output, cutting down on I/O's. The gates permit a small amount of internal logic to reshape itself into many different operating modes. Six of these gates are used at each of the 4-bit positions on the chip (see B [in the schematic ]). EDN breadboarded with these transmission gates (from RCA's COS/MOS family) and found that they permit easy mechanization of trick circuits that might be impossible otherwise. They are really analog gates, for they faithfully pass analog signals as well as digital. A pair of complementary MOS devices—one p channel and the other n—presents either low or high impedance in a circuit path (see C [in the schematic ]). Impedance looks the same in both directions, so unlike ordinary digital gates, the transmission gate passes signals in either direction. In the processor, control signals command transmission gates to open and lose various signal-path combinations selectively. They "electronically rewire" the chip. For example, the transmission gate on the single I/O line in B opens so that external information is read into the data flip-flop. Or other gate combinations open and close to read data out of the flip-flop on the same I/O line. Still other combinations are switched to allow a new input in the I/O line to be added or subtracted with the flip-flop's existing contents. Co-author Dingwall says another COS-MOS feature that keeps chip size down is functional or relay-type logic. This implements easily in COS-MOS and performs Boolean combinations in one stage instead of two stages of NAND gates. |
