FROM EDN EUROPE: IP provider mounts structured ASICs on standard-cell libraries
By Graham Prophet, Editor -- EDN, May 11, 2006
Lightspeed Logic was previously a vendor of structured-ASIC silicon products—chips that, with some similarity to earlier gate-array devices, provided an array of logic functions that achieved final functionality when the vendor added a small number of application-specific metal layers on the devices. Now the company has changed focus to being an IP provider.
With its products, you can still design devices that offer arrays of flexible logic, ready for final mask-programming: the difference is that you build those base arrays on other vendors' standard-cell SoC, ASSP or ASIC processes using Lightspeed's IP.
You can achieve logic density about 80% of that of standard-cell devices, the company says, as it builds its arrays using standard library elements comprising optimised cells. Lightspeed also says that 90 to 95% of signal nets are immune to signal-integrity problems, again due to the use of pre-characterised structures.
The company employs high-drive strength cells from silicon vendors' libraries, reducing integrity problems; plus, the use of a regular array results in a more easily verifiable power grid. As a user, you can build a single ASIC-like product on a standard-cell technology, that will support several of your designs—reducing up-front design costs—and hold them to await final mask-configuration. The system comes with an automatic test-generation routine for which the company claims 98% stuck-at-fault coverage, and is available for 130- and 90-nm processes, with 65 nm to follow.
