Three-phase sinusoidal-waveform generator uses PLD
Five ICs substitute for electromechanical three-phase source.
Eduardo Perez-Lobato, University of Antofagasta, Antofagasta, Chile; Edited by Brad Thompson and Fran Granville -- EDN, October 12, 2006
Using the circuit in this Design Idea, you can develop and implement a lightweight, noiseless, inexpensive, three-phase, 60-Hz sinusoidal-waveform voltage generator. Although targeting use as a circuit for testing power controllers, it can serve other applications that require three sine waves with a 120° relative phase difference. A 22V10 PLD (programmable-logic device) at IC1 generates three three-phase, 60-Hz, square-wave voltages. Internal register IC1 and Q0, Q1, and Q2 bits set the Q3 bit to lead the Q4 bit by 120° and set the Q5 bit to lag behind the Q3 bit by 240° (Figure 1). Setting IC1's clock frequency to 748 Hz produces 60-Hz outputs at Q3, Q4, and Q5.
IC1's three square-wave output voltages—Q3, Q4, and Q5—drive IC2, IC3, and IC4, three Maxim MAX294 eighth-order, lowpass, switched-capacitor filters to produce three 2V sinusoidal waveforms (Figure 2). When you connect IC5, a common 555 timer as an astable oscillator, it produces a 6-kHz, TTL-level source that clocks all three filters at 100 times the desired 60-Hz output frequency. A 100-nF dc-blocking capacitor at each filter's output ensures that the three-phase outputs swing from +2 to –2V with respect to ground. Note that each filter inverts its output and introduces a 180° phase shift with respect to its input square wave.
Figure 3 depicts the phase relationships among IC1's outputs and yields Boolean equations (Table 1). The equations translate into set/reset signals that produce 64 logic states when you apply them to a 6-bit sequencer block in IC1. Outputs Q5, Q4, and Q3 represent the three most-significant bits, and Q2, Q1, and Q0 represent the three least-significant bits. After translation, an emulated Basic program (Listing 1), produces fuse-programming code for IC1's sequencer and logic states. Although only 16 logic states define the sequencer's functions, its remaining 48 states also require definition to avoid anomalous operation.
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748 Hz??? The timing diagrams look like the circuit uses divide-by-12 and so you'll get 62-1/3 Hz with a 748 Hz input.
If you use 720 Hz you'll get 60 Hz out.
It can be done with only 4 FF (instead of six):
First divide the 720 Hz by two to drive a 3-stage as taps (one inverted) of the Johnson counter as Mark Johnson counter operating at 360 Hz to get the output just suggested or by direct logic synthesis, using Q3, Q4, and Q5 as three of the state variables.
Allen Tracht - 2007-8-1 10:44:00 PST -
Couldn't you do the same functionality as the PLD with 3 D flip-flops set up as a Johnson Counter?
Mark Atchison - 2006-1-11 09:54:00 PST
