Tool generates HDLs directly from Simulink
By Michael Santarini, Senior Editor -- EDN, September 19, 2006
The folks trying to model multiple DSP functions to implement in FPGAs or ASICs using MathWorks tools will be happy to learn that the company's latest release, Simulink HDL Coder, automatically generates cycle-accurate, bit-accurate Verilog or VHDL directly from Simulink. Before this announcement, users created Simulink-algorithm-based models of DSPs in Simulink and then had to recode them in VHDL to employ the DSP functions in FPGAs. That step will now be unnecessary, according to Ken Karnofsky, director of marketing for the signal-processing- and communications-products group at MathWorks.
Sudhir Sharma, HDL-product-marketing manager says that users can employ the bidirectional tool to both transfer and cosimulate Verilog and VHDL into Simulink models. "You can verify testbenches, intellectual-property blocks, and legacy code in HDL in Simulink, speeding simulation," he says. Because the tool can generate HDL directly from Simulink, you can also run the HDL in FPGAs, representing a big step toward allowing software engineers to directly program designs in FPGAs. Sudhir points out, however, that the tool doesn't replace a hardware engineer, because synthesis, routing, and other FPGA-programming functions are still necessary for the FPGA to work properly. Simulink HDL Coder is available for the Windows, Unix, and Linux platforms. The MathWorks offers it in a perpetual license with prices starting at $15,000. Users must also purchase a separate Simulink license.
