8051 core sports hardware arithmetic extensions
By Robert Cravotta, Technical Editor -- EDN, May 8, 2006
Ramtron’s VRS51L2070, the latest device in the Versa 8051 microcontroller family, integrates a single-cycle, 40-MHz, 8051-based core with 4 kbytes of SRAM, 64 kbytes of in-system-and in-application-programmable flash; a JTAG programming/debugging interface; and digital-signal-processing extensions. The multiply/accumulate/divide unit includes a 32-bit barrel shifter that can perform single-cycle, 16-bit signed multiplication and 32-bit addition, and it can perform a 16-bit, signed division in five cycles. You access the multiply/accumulate/divide unit through the 8051’s SFRs (special-function registers).
To lower costs of embedded designs, the VRS51L2070’s internal oscillator supports 40-MHz operation with 2% accuracy. The device includes eight PWMs with 16-bit adjustable resolution. Two pulse-width counter modules enable event-duration measurement. The integrated SPI can support transactions as fast as 20 Mbps that are adjustable from 1 to 32 bits. Each UART incorporates a dedicated baud-rate generator with 16-bit resolution and 4-bit micro-baud-rate adjustment. Other peripherals include an I²C, three 16-bit timers/counters with three timer-capture inputs, a watchdog timer, and 49 interrupts that share 16 interrupt vectors. The VRS51L2070 is currently available for sampling and costs less than $4 (10,000) in a QFP-64 package.
