DFM-tool start-up claims big power and yield gains
By Michael Santarini, Senior Editor -- EDN, May 15, 2006
EDA-DFM (design-for-manufacturing) start-up BlazeDFM has announced its first tool, which it claims will reduce leakage power by as much as 40%, reduce leakage variability by as much as 60%, and improve timing by as much as 10% without the need for changing the layouts of 90- and 65-nm IC designs. Chairman and Chief Technology Officer Andrew Kahng, a University of California—San Diego professor, started the company, along with one of his grad students, Product Architect Puneet Gupta. The third co-founder, Vice President of Marketing Dave Reed, is an EDA-industry veteran. The company also brought on former Forte Design Automation Chief Executive Officer Jacob Jacobbson to serve in the same post at BlazeDFM.
Reed says that more than 20 companies claim to be in the DFM market. However, BlazeDFM concentrates on only a subset of that market: electrical DFM. “DFM understands the things designers care about: power, performance, parametric yield, and cost,” says Reed. He claims that other companies have only obliquely addressed these topics. “When you look at the parametric-yield issues, as Blaze DFM does,” he says, “you can reduce by six months to a year the time it takes to get into volume production at accept-able yields, and you can reduce leakage power by 20 to 30%.”
The company's tool, Blaze MO, runs concurrently with physical-verification tools. Users input GDSII (Graphic Design System II) and industry-standard formats, such as Verilog, LEF/DEF (library-exchange-format/data-exchange-format), DSPF/SPEF (detailed-standard-parasitic-format/standard-parasitic-exchange-format), .lib, and SDC (Synopsys Design Constraint) files into the tool. Blaze MO analyzes the layout and gate-length variability, or “slack,” within the rules of a given foundry and creates an annotation layer in the GDSII to direct commercial OPC (optical-proximity-correction) tools to make adjustments to the design. “We put our annotations in a layer in the GDSII file, and, when it gets into manufacturing, the RET (reticle-enhancement-technology) tools can use those annotations to direct reticle enhancement,” says Reed.
OPC tools cannot directly read the annotations, so OPC engineers must manually input them into the OPC tool of choice. Blaze MO has run silicon with both Mentor Graphics and Synopsys OPC tools with similar results. OPC tools typically adjust layouts to ensure that each feature has the right size and shape and thus prints well in manufacturing. “Blaze tells what targets to hit on a transistor-by-transistor basis within the allowed processor range,” he says. Blaze MO doesn’t swap out custom cells for standard cells. Instead, the subtly altered shapes on a design have a profound impact on the design.
“To have a viable DFM offering, you need to offer value to both design and manufacturing,” says Reed. “Blaze MO can help foundries make the same process look better to their customers without adjusting the equipment. It is possible to offer a half-node to customers—a process that is less leaky than, say, a foundry’s standard 90- nm process.”
