Synopsys DFM tools tackle first-order issues
By Ron Wilson, Executive Editor -- EDN, July 24, 2006
Following a pattern that has emerged in recent EDA industry conversation about DFM (design for manufacturing) tools, Synopsys went on record today with the three now-obligatory tools: LCC (lithography compliance checking), CMP (chemical-mechanical polish) checking, and CAA (critical-area analysis).
The three tools taken together do not begin to cover all the important sources of variation in 90-nm and finer geometries, according to industry experts. TSMC, for example, cites more than 2000 independent sources of potential trouble. But the tools do, according to Synopsys, capture the first-order problems.
"Our first step is to prevent catastrophic failures on wafers that are processed within the process window," says Srinivas Raghvendra, the company's senior director of business development. With chip failure all but ruled out, designers can lump variations from all the other sources under the heading of parametric variation and deal with them using the statistical-timing tool Synopsys also announced today (see "Is Synopsys' statistical-timing tool ready for prime time?").
The company appears to trust this approximation better for metallization than for active-area features. Raghvendra suggests that cell designers will still have to make accurate statistical estimates of the transistors’ effective channel width and length, based on their geometry and surroundings, probably by using feedback from process engineers and test chips or directly employing the foundry’s TCAD (technology CAD) models. But if the three new tools can liberate the users of cell libraries from the growing threat of the first-order sources of variation, they would almost restore determinism to cell-based design.
The first of the new tools, LCC, inspects GDS-II files using a rapid-computation model of the lithography process, calibrated with foundry data. This scan predicts the actual shapes the mask features will produce, across the focus window of the lithography step. It then examines these features against a rule set to detect pinch-off, end-shortening, bridge, and other faults that could occur with a reasonable probability.
The normal output of the device is a color-coded die map: green for areas that pass, yellow for areas of concern, and red for trouble spots. Design teams that are knowingly pushing the litho rules can look under this graphic presentation at a numerical database that will give them actual predictions of critical dimensions.
Designers can then invoke an auto-correction tool, which is based on extensive, process-dependent heuristics, to deal automatically with the majority of the problems—adding space between lines, moving edges or corners, and other such reasonable measures.
The second tool, CMP Check, performs a similar model-driven scan of the metal masks to look for known sources of variation in the CMP process. Using its process model, derived from the foundry’s TCAD models but again abstracted for quick computation, the tool builds a thickness map of the die, which it then passes on to the RC extraction tool to substantially account for variations in resistance and capacitance due to metal dishing and thinning. In essence, the tool eliminates yet another set of variations by more accurate prediction of the results of the process.
The third tool, CAA, is probably the least important of the three below 90 nm, but designers are still requesting it, according to Raghvendra. The CAA tool also scans the metal masks, looking this time for areas in which a particle of critical size could potentially cause a short or open in the metal. The tool flags such areas, and the prudent designer will go back to increase feature spacing or width. This, of course, renders the design relatively immune to the more probable small-particle defects. Because particle defects play a secondary role in yield at 90 and 65 nm, this is not a critical step, but still a useful one.
Synopsys bears the responsibility of working with foundries to gather data on specific processes—and in some cases specific lines—to incorporate into their models. Synopsys customers then receive these models. Obviously this will only be practical in cases where the foundry’s TCAD results are changing relatively slowly compared with the progress of a physical chip design. So widespread adoption of the tools, even by the small minority of design teams now working at 90 and 65 nm, could mean a significant restriction in the degrees of freedom process engineers have to center processes for major customers or simply to tweak problem areas. Yet the benefits are likely to outweigh this issue most of the time.
