Is DFT the key to reducing test costs?
By Sally Cole Johnson, Contributing Writer -- EDN, September 1, 2006
In an era when semiconductor costs are outpacing market growth, there's no doubt that the industry would like to see faster automatic test equipment (ATE) development that carries a low price tag.
A big roadblock to achieving this is the "wall" between design and test, contends Jim Healy, president and CEO of LogicVision, a yield learning company that works with top ATE players. Another challenge is that semiconductors are becoming increasingly complex, which is keeping test costs high.
One possible way to reduce costs may be right under the industry's nose, Healy says. But organizational dynamics are preventing it from being implemented. He says that technology and methodologies exist to trim the cost of test by at least 50 percent—simply by integrating ATE with supporting design for test (DFT). This would help provide real-time, at-speed, built-in test capabilities at probe and final test, he explains.
So what's the holdup? Part of it has to do with shrinking time-to-market requirements and product life cycles of six to nine months for system-on-a-chip (SoC). The short timelines are hard to accomplish because SoCs are complex, expensive, time-consuming to test and difficult to yield.
Major ATE players Advantest, Teradyne and Verigy say that driving down the cost of test is a huge challenge. "The semiconductor industry is in a dilemma, facing the need to accelerate development of state-of-the-art testers to meet rapidly changing and expanding needs of complex, diverse SoC test, while simultaneously lowering test costs," explains R. Keith Lee, Advantest America's president and CEO.
Cooperation is needed between electronic design automation (EDA) and ATE to bring down the wall between DFT and ATE, according to Verigy's Ajay Khoche and Martin Fischer, both Advanced Test Methodologies consultants.
