A gem in the rough?
By Michael Santarini, Senior Editor -- EDN, February 8, 2006
The conference is one of the most daunting assignments in the profession of trade journalism. One must scramble to cover panels, keynotes, and technical-paper presentations while working to find proprietary news tidbits. In one day you can attend four or five different program sessions, but only about one in 10 will actually turn up something novel, let alone true news.
But sometimes even the most boring panel, if you can stay awake and resist the temptation to throw yourself on your pen, can produce a sentence or two that instantly wakes you up and sends you scrambling to make sure your tape recorder is running.
Such was the case at a panel I was covering at DesignCon on Tuesday. The panel was so boring and the moderator so controlling that about 9/10 of the way through the session, one of the panelists spoke up, pleading with the moderator to stop asking his own questions and allow folks in the audience to participate. The moderator ignored the suggestion and continued to ask his line of questions until the end. The panel and moderator will remain nameless, and I certainly won't bother recreating the minutes of the discussion as I'm not a sadist.
But I will share a news gem that came out of it: Synopsys is developing a formal equivalence checker to compete with Calypto Design Systems. Indeed, a Synopsys official on the panel said Synopsys customers are beta testing a formal-verification tool that verifies that an RTL or gate-level design is equivalent to its system-level specification.
Had the moderator given the audience a few minutes, or had the executive stuck around a tad longer, I could have chased it down. And I will once I'm done covering the rest of the show. But I certainly have more questions.
Does this mean Synopsys is going to take SystemC seriously, again? Does it mean the company has a new language brewing? Does it mean Synopsys is developing new tools in ESL (electronic-system level) design beyond SystemVerilog?
What would a Synopsys entrance to the market mean for startup Calypto? Did this play a factor in Calypto's recent management shakeup? Are there other reasons for the shakeup?
Some say that the problem Calypto—and now Synopsys—is trying to solve is too complex. If that proves to be true, it would be sad, because the ESL advocates say that in order to make ESL viable and to drive design to the next level of abstraction, the industry will need a way to ensure that what you produce in system-level language can be reproduced, but in more detail, at the RTL or gate level. It is essential to checking the results of a system-to-gates synthesis tool like Forte Design Systems offers.
We'll see. I'm hoping this gem will turn into a diamond mine for the electronics industry.
(see the update on this opinion)
