Cadence-Led Initiative Seeks Low Power Standard
By Michael Santarini, EDN -- EDN, May 22, 2006
Cadence Design Systems Inc. is heading up an ambitious effort to devise a standard power format that will allow tools across the design flow to communicate via a common format and better deal with IC power management as it becomes more complex with every new process node.
Cadence with the help of its "Power Forward Advisor" partners -- AMD, Applied Materials, ARM, ATI Technologies Inc., Freescale Semiconductor, Fujitsu, NEC Electronics, and TSMC -- plans to create in its Power Forward Initiative (PFI) a common power format (CPF) that will allow designers to address power issues early in the design process and according to Chi-Ping Hsu, corporate VP of synthesis solutions, will "set the foundation for a new wave of tool innovation."
"If you think about the last 10 or 15 years, we've been talking about physical effects and its impact on timing," said Hsu. "Now this is the beginning of the infrastructure for advanced low power design. It will be a five to 10 year journey for the industry to move on. By having this foundation up front we've shortened the time it will take for those innovations to happen."
Eric Filseth, the company's VP of product marketing, said that power is becoming the top problem in CMOS based design. He points to recent IBM CTO Bernard Meyerson's presentation, in which Meyerson illustrates how CMOS has now reached the peak level of modular heat flux (14watts/cm2) that made in the late 1970s the industry drop bipolar as the mainstream IC design material in favor of CMOS.
"CMOS had all kinds of undesirable characteristics in those days: it was prone to latch up, didn't have any gain but it consumed orders of magnitude less power than bipolar, and that's the reason the industry switched," said Filseth. "The same thing is happening again but now there isn't an obvious materials based solution that we can switch to."
Given that, the EDA industry has to do its part to stretch out the life of CMOS and come up with better ways to manage power. Manufacturing and equipment firms have also made great strides in dealing with low power by employing MTCMOS (multi-threshold CMOS), low power libraries, thicker oxide transistors, and SOI.
Now Cadence believes the CPF will make huge strides in power management from the design perspective.
Much like there is a standard timing format, SDC (Synopsys Design Constraints) that all tools can access, there needs to be a similar format for power. "In the low power design world, this stuff doesn't exist," said Filseth. "If you want to specify something as simple as one half of the tool has to run at this supply voltage and the other half has to run at a different supply voltage, there isn't a standard way to do that."
Filseth noted that power management requires much more complicated specifications. For example, mobile designs often run in mixed modes where parts of the design are always active, other parts are in asleep and still other parts are not running at all. The CPF would need to describe all of these modes.
"The kinds of things people are doing to save power have to be defined pretty early in chip development," said Filseth.
That's why the abstraction level for this specification is for the RT level and above, said Hsu. "Most of the infrastructure today for power is at the physical implementation level," Hsu said. "What's unique here is we are bringing it all the way up to the RT and architectural levels. It's really linking the simulation, verification with implementation tools."
The company has tapped Hsu, the technology brains behind Avanti and former CEO of synthesis company Get-2-Chip, to organize the format's design effort. Hsu has organized a preliminary specification from 11 groups at Cadence. Hsu said that while smaller companies have done work in particular areas mostly in implementation tools, no one has attempted to come up with a set of requirements across design, verification and implementation.
"The knowledge that is required in each of these spaces if very deep," said Hsu. "We have pulled together key architects from all these disciplines to study and strategize what to do."
The company is only working with its "Power Forward Advisors" to create a first draft of CPF but plans in early 2007 to open up the effort to others via a "Power Forward General Membership." The company has set aggressive goals on delivery and hopes to hand off the CPF to an independent standards body, like IEEE or Si2, by 2008.
Jan Willis, senior VP of industry alliances, said it is restricting design of the first draft to the Power Forward Advisors to expedite the design effort. The company has not rejected the idea of adding other firms to the advisor groups or for that matter companies that are already fielding power tools.
Creating standards in EDA is akin to herding cats. But Willis said the customer and partner positive reactions to the initiative plans have shown it is a worthwhile endeavor.
