DesignCon reporter's notebook
By Michael Santarini, Senior Editor -- EDN, February 8, 2006
Thus far, DesignCon panels have turned up two scoops.
Synopsys revealed yesterday that it is beta testing a new C-to-RTL equivilance-checker technology. This morning Rindert Schutten, director of Synopsys' system-level solutions group, shed more light on the release, telling EDN that the technology, still under development, checks the equivalence between pure C and RTL code. Beta testing is still underway, and the company has not set a product release date, as the technology is still rough, he said. Although the technology currently compares C to RTL, Synopsys may turn it into a SystemC to RTL equivalence checker, Schutten added. A SystemC version would seemingly put Synopsys in competition with startup Calypto Design Systems, which offers SLEC.
Tera Systems has apparently gone out of business, but the technology it developed is alive and well and still serving as the front end of LSI Logic's RapidChip structured ASIC flow. Scott Peterson, director of RapidChip Methodology, said LSI "has the code" and is still using Tera as a front end. Rumors that Tera may have quietly closed its doors first appeared in John Cooley's designer forum, DeepChip.com.
