Cadence spins "secure" DFM model, makes custom layout litho savvy
By Michael Santarini, Senior Editor -- EDN, February 13, 2006
Releasing the first fruits of its DFM (design for manufacturability) partnership with ASML, Cadence Design Systems this week will unveil a new process model for sharing sensitive IC-manufacturing data with design tools and a suite that makes the Virtuoso full-custom layout tool lithography savvy.
The new suite, called Virtuoso RET (reticle enhancement technology), includes four tools, all of which run from a new lithography model, called PMF (process modeling file), that Cadence and ASML developed to characterize the intricacies of the ASML lithography process.
PMF is "the secure courier of detailed and confidential manufacturing capability that seamlessly integrates to the design environment," said Mark Miller, Cadence's vice president of business development. As such, it is Cadence's candidate for an eventual industry-standard file format for passing data from manufacturing to design. DFM is so new the industry hasn't yet called for a standard.
Miller said PMF contains exposure info such as reduction ratio, exposure wavelength, and NA (numerical aperture); illumination details such as off-axis illumination type and sigma; resist process specifics; and mask type and specifics.
Virtuoso RET represents half of step No. 1 in Cadence's four-step DFM product roadmap, Miller said. That first step, making layout tools aware of lithography, will be completed when Cadence offers similar RET functionality for its Encounter ASIC and SOC (system on chip) flow. The company then plans to offer tools for batch OPC (optical proximity correction) treatment, layout-to-manufacturing rule checking, and then litho process development. All of these tool suites will use the Cadence/ASML PMF as a common model.
The new Virtuoso RET aims to return predictability to the design-creation process and make layout tools implement litho-savvy traces in design, rather than having to go back and fix a lot of traces after running a batch OPC, Miller said.
"You make the authorship smarter and more aware of lithography, so later when you try to go through that batch treatment, the effectiveness of it is much higher," he said. "It makes it easy to treat, convergence is much higher, and it makes it more predictable."
The first tool in the suite, Virtuoso RET Imager, is essentially a simulator that superimposes over a Virtuoso-drawn layout an outline or contour (derived from the PMF model), which shows how the layout would look if manufactured without modification.
The second tool, Virtuoso RET Verifier, is much like a design-rule checker except that it doesn't do a traditional geometric edge-to-edge spacing check. Instead, the tool performs a full litho simulation, testing shapes produced by the Virtuoso RET Imager tool against user-specified lithography rules to flag violations that may affect yield, Miller said. "It flags variances between contour lines that are generated versus the original source data," he said. "It is the programmatic way to check the magnitude of the number of errors and violations you have." The tool also flags layout areas that have rule violations and groups the violations in a separate menu.
The third tool, Virtuoso RET Designer, allows layout engineers to do quick OPC and RET runs on small sections of the layout, as opposed to waiting for the results of a full batch OPC run on an entire design layer. The tool can do OPC-,model-, or rules-based RET on small portions of a layout, which helps layout engineers determine what treatment to employ for a given part of the layout, Miller said.
The fourth tool in the suite, Virtuoso RET Analyzer, targets layout experts and even lithography-process and modeling-development groups that want to quantitatively analyze Virtuoso RET Imager results in order to evaluate, compare, and tune RET approaches. "After you think the design is litho clean, it analyzes the layout to see what happens if there is variation in the litho process," Miller said. "It will look at things like the amount of energy that is deposited at a particular spot in the resist or if the stepper is a little bit out of focus." Users can also generate intensity maps to find, for example, overly resilient scatter bars—the fine traces layout engineers place in their layouts to calibrate batch OPC runs. Traditionally these scatter bars are so fine that they are not picked up in the printing process, but if they are they can cause shorts and lead to massive failures.
The Virtuoso RET suite starts at $100,000 with RET Imager and goes up as customers require the added functionality of Virtuoso RET Verifier, Virtuoso RET Designer, and Virtuoso RET Analyzer. The company did not provide a timetable for when similar technology will be available for the Encounter ASIC and SOC tool flow.
