Silistix introduces tools to take asynchronous design mainstream
By Michael Santarini, Senior Editor -- EDN, January 16, 2006
EDA and IP startup Silistix is unveiling tools that it claims will free IC designers from slavery to a single system clock by allowing them to stitch together IC design blocks with the company's asynchronous IP bus.
Asynchronous design has thus far only been a practical methodology for very advanced designers, but with its IP and EDA combo, Silistix believes it can make the methodology more accessible to mainstream ASIC and SOC (system-on-chip) designers. The company introduced itself and its CHAIN fabric asynchronous-bus IP last December. Now it is releasing the tools that implement the bus.
The ChainWorks flow consists of two tools that plug into the traditional ASIC/SOC design flow and a library (click here for a design-flow diagram).
The first tool, CHAINdesigner, is a graphical-entry tool that helps users arrange IP and proprietary logic blocks in their designs, then interconnect them to come up with a desired network topology. Users feed the tool Verilog, SystemVerilog, or SystemC. "That will essentially define initiators and targets as wells the ports for the initiators and targets," said David Fritz, the company's vice president of marketing. "The tool has a graphical user interface that people prefer to use because it gives you a much more formal mechanism for visualizing, understanding, and designing the interconnect."
The GUI has been "well received" by interconnect designers, and a future version will allow them to embed notes in the design to better monitor progress and describe intent, he said.
After users design a topology, the tool generates Verilog and SystemC models and testbenches for simulation, as well as constrained CHAIN netlists for input to CHAINcompiler. "You can't really represent a self-timed circuit in Verilog, so we have to have our own internal format to do that," Fritz said.
After designers have verified their design topology, they can then use the CHAINcompiler asynchronous synthesis tool to implement the design, interconnecting the various blocks with the company's CHAIN fabric bus. CHAINcompiler uses a proprietary asynchronous interconnect components library called the CHAINlibrary to produce the structural netlist.
"CHAINcompiler will take the library components and combine them to construct your interconnect network," Fritz said. "It will then generate a structural netlist that goes into conventional logic-synthesis tools such as Synopsys' Design Compiler, it will generate static-timing-analysis scripts, place-and-route hints critical for self-timed circuits, and test patterns."
The first release supports scan insertion for interconnect ports, while a future release will include partial-scan BIST (built in self test).
The company built the flow so that users can run iterations between ChainWorks and synthesis, timing analysis, place and route, and extraction, Fritz said. However, most users only need to go through the flow once, he added.
While the company believes the flow will open up asynchronous design to mainstream use, it doesn't yet have any customer tapeouts to report. It has, however, developed a test chip in house and claims that unnamed customers are using the tool on current projects.
"On our test chip, the longest wire on our interconnect was 1 mm," Fritz said. "Even with weak drivers, we got a half-gigabit transfer rate with a single wire. Because of that, when it comes time to iterate through this, the throughput in the interconnect itself is such that it is very easy to get the timing closure of the interconnect. What we've been finding is you go through this once and you are done. It won't always be the case, especially in designs that require a lot of interconnect and [have a lot of] crosstalk, but in general the number of iterations is significantly reduced. It's one of the advantages of the self-timed design."
The test chip also proved that the company's tools implement structures that are Spice-accurate, Fritz said.
Even though Silistix is essentially offering both IP and EDA tools, the company is employing an EDA sales model, in which users license the ChainWorks tools and get the IP that those tools help to implement at no extra charge. Fritz declined to give exact prices for the tools, but said CHAINcompiler would likely be priced similar to Synopsys' Design Compiler, while CHAINdesigner will likely be comparable in price to Mentor Graphics' ModelSim simulator.
