News analysis: Is Synopsys' statistical-timing tool ready for prime time?
The company is taking a measured approach to adding statistical timing technology to its powerhouse PrimeTime tool.
By Michael Santarini, Senior Editor -- EDN, July 24, 2006
With the release this week of its long-anticipated statistical-timing-analysis technology, Synopsys hopes to fend off threats from IBM, Extreme DA, and Magma Design Automation and retain PrimeTime's status as the industry's de facto standard for timing-analysis signoff. But ironically, the new tool add-on, called PrimeTime VX, has the earmarks of a technology that may not yet be ready for prime time.
Static timing analysis has long been the heart of the IC design flow—the tool that most IC design groups use to converge on timing. Indeed, static timing analysis is somewhat of an anomaly in the EDA industry in that pretty much all design groups, foundries, IDMs (integrated device manufacturers), and EDA vendors standardize on one tool and only one tool.
For the last half decade, that de-facto-standard signoff tool has been Synopsys' PrimeTime. PrimeTime became the standard after Synopsys purchased Viewlogic and subsequently killed the EDA industry's then de facto timer, Motive. The demise of Motive didn't cause a huge customer backlash because PrimeTime truly is a better tool.
According to research firm Gartner Dataquest, Synopsys boasted a 93% share of the timing-analysis market in 2004.It's interesting to note that while few IC designers have complained about the functionality of the tool, Synopsys has taken plenty of heat from EDA competitors and customers alike for not opening up its Liberty timing package, and specifically its .lib format. Eventually, after great pressure and bad press, Synopsys made the format available (but maintained control of its evolution), and in doing so allowed other vendors to standardize on it. But now that move has allowed timing startups to challenge PrimeTime's position as the anointed signoff timer, especially as the industry looks to statistical timing for next-generation designs.
As processes continue to shrink, giving engineers exponentially more gates to work with and complicating the manufacturing process, pure static timing analysis is becoming insufficient. At previous process nodes, a static tool would define worst- and best-case boundaries for performance, and designers just had to be sure their circuit timing fell between those boundaries. At the 65-nm node, those boundaries become far too pessimistic, or far apart; they don't accurately reflect the true timing of circuits. Thus designers using pure static analysis today leave significant performance on the table.
A few years ago, researchers from IBM and academic institutions showed up at DAC and timing-analysis conferences describing promising results from statistical methods. Statistical analysis models gate and wire delays as probability distributions with complex correlations. It also predicts chip performance and parametric yield as probability distributions.
Last year IBM finally fielded its offering in this area, Einstimer Statistical. Newcomer Extreme DA had introduced its own statistical tool a few months earlier. The IBM statistical-analysis group won best paper at DAC two years ago and took home EDN's Innovator of the Year award for 2005. In addition, Einstimer itself took the top award in the EDA (Design and Implementation) category in the EDN Innovation Awards.
This year, the pressure on Synopsys has grown even more intense, as arch-rival Magma has also announced statistical-analysis capabilities. However, Synopsys hopes it can leverage its established user base in static timing tools to keep PrimeTime in its spot as the industry's chosen signoff timer.
The company will announce this week that it has made both PrimeTime and its parasitic extraction tool, Star-RCXT, "variation aware" and statistically savvy. EDN broke the news that the company was readying a statistical tool earlier in the year (see "Synopsys spins new physical model, preps statistical timer").
With the new PrimeTime VX, the company is taking what appears to be a quasi-statistical approach, in that users will run traditional static timing analysis on a large majority of a given design, reserving statistical timing analysis for the most performance-critical nets.
The tool employs a mix of analytical and sample-based statistical methods. "Both methods have advantages and disadvantages," says Ahsan Bootesaz, vice president of engineering for Synopsys' implementation group. "By having both we can offer the best possible solution."
Steve Smith, senior director of marketing for the company's implementation group, adds that PrimeTime VX is an evolutionary step forward. It helps introduce users to a new methodology via a new feature while not completely changing the technology they are used to, he says.
Synopsys has been tracking timing needs at each node, and at 65 nm the company sees those needs changing. "We're seeing tapeout with PrimeTime and are seeing that customers [designing at 65 nm] are doing OK with current timing-signoff methodology, which uses timing margins," Smith says. "But what we're hearing increasingly, especially with high-performance designs, is a need to unlock a better prediction of the real performance."
Variation awareness
To make the flow variation-aware, Synopsys had to adjust some other tools, Smith says. The company modified its Liberty library format for CCS (composite current source) modeling. This gives the PrimeTime VX technology timing models based on device variation. The company also created a variation-aware add-on for Star-RCXT, which will be offered under a new name, Star-RCXT VX. The add-on allows the tool to perform "sensitivity-based extraction" to produce parasitic models based on interconnect variation, Smith says.
Users will input their design netlist and process characteristics into Star-RCXT VX, Smith says. "One of the big things that Star-RCXT VX can do now is to replace what used to be multiple, corner-based RC extraction runs—to model the min/max variations of various timing, temperature, and voltage conditions—with a single run. It's a big advantage with run time and generates this variation-based parasitic data set."
The extraction accounts for the voltage and temperature corners, but does not yet account for time-dependant temperature. Instead, it works on worst-case parameters of –40 to 120°C.
The tool then runs extraction and produces DSPF, SBPF, SPEF, and Spice for the old static PrimeTime, along with DSPF, SBPF, SPEF, and Spice with variation sensitivity for PrimeTime VX.
The data that goes into the statistical flow exist in two forms, Bootesaz says. "The first is basically the device variation of different parameters for the transistors inside the cells," he says, noting that engineers will feed that information into PrimeTime VX. "The second type of data that comes from Star-RCXT VX is the variation of the RC. We take both those into PrimeTime to do the analysis."
Because many of these parameters and variations can change weekly or monthly in a fab, Synopsys does not embed the distribution data in the library. Rather, users must get the actual distribution data in a Spice file from their targeted fab and input those parameters manually. "That way we can have different distributions without changing the library data," Bootesaz says.
Users will run the analysis at the nominal process points (at two different temperatures and two different voltage points) to come up with a list of critical paths. "Then you can do fine-grained statistical analysis on those paths," Bootesaz says.
For those paths, the tool then essentially displays a new, tighter set of parameters.
With the new device and interconnect models, PrimeTime VX produces results within 5% accuracy of Spice, as gauged with Monte Carlo simulation, according to Smith.
To illustrate the gains the tool delivers, Smith shows an example in which static timing came up with a worst-case, corner-based performance target of 404 MHz, whereas PrimeTime VX showed a statistical-based 474-MHz slack with a 99% probability. That translates to a 16% performance increase, although Smith readily admits that the tool will not always show timing improvements of such magnitude.
While most engineers won't use the statistical-analysis functions for entire chips—instead using them specifically for critical paths—the tool can perform full-chip statistical analysis overnight, Smith says.
Reaction
By giving designers tried-and-true static functionality while at the same time introducing them to new and probably unfamiliar statistical methods, Synopsys is taking what seems like a reasonable incremental approach. However, the release has some of the earmarks of a technology that isn't 100% ready.
For example, Synopsys uncharacteristically did not produce a high number of endorsements. The company publicized only one, attributed to Philippe Magarshack, group vice president and general manager of central CAD and design solutions at STMicroelectronics. This seems odd given PrimeTime's enormous market share. Moreover, the company hasn't yet announced a price.
Industry observers will recall that the last time Synopsys acted in this manner was a few years back when it released Route Compiler (code-named Route66). Later, the company either shelved Route Compiler in favor of Avanti's Apollo, or, because Route Compiler failed, became more eager to purchase Avanti. To Synopsys' credit, TSMC tells EDN that it has checked out PrimeTime VX and endorsed it for its new 65-nm reference flow. (Magma's statistical tool has received the same blessing from TSMC.)
Synopsys maintains that the two tools are indeed ready for use today despite the fact that the company withheld pricing from its release. [Update: After DAC, Synopysys told EDN that the price for the PrimeTime VX add-on to PrimeTime is $122,500 for a one-year subscription, while the Star-RCXT VX add-on is $122,500 for a one-year subscription.]
Regardless, Synopsys' entry into the statistical game underscores that the industry is accepting its need for statistical timing analysis. EDN will monitor the technology's progress to see if, for example, engineers need to run statistical analysis on entire designs instead of only the critical nets.
Synopsys is hosting a lunch with STMicroelectronics, another (unnamed) customer, TSMC, and consortium STARC at DAC on Tuesday, July 25 at11:45 am PDT.
