Lithography-savvy IC router circumvents third parties
By Michael Santarini, Senior Editor -- EDN, July 17, 2006
Physical-IC designers now have an alternative to Cadence, Synopsys, and Magma physical-design flows: Sierra Design Automation’s new detailed router tool. The router joins the company’s previous offering, Pinnacle, a combination floorplanner, physical-synthesis, and clock-tree-synthesis tool. The new tool, the Olympus-SOC (picture) (system-on-chip) netlist-to-GDSII (Graphic Design System II) suite, competes directly with Cadence’s Encounter, Synopsys’ IC Compiler and Magma’s Blast and new Talus RTL-to-GDSII suites.
Pinnacle supports multimode design, in which ICs have, for example, off, low-power, standby mode, and full-performance modes. It is becoming common for advanced-IC designs to have several blocks, each of which can operate in multiple modes. Thus, designers need to account for multiple combinations of mode switching. Pinnacle users can check the impact of multimode and multiprocess corners on timing and power and signal integrity, but the availability of Olympus eliminates the need to pass that information to a third-party detailed router.
Shankar Krishnamoorthy, chief technology officer of Sierra, says that there hasn’t been a significant breakthrough in routing since Magma introduced Blast about eight years ago. Routing needs have evolved, he says, and GDSII netlists now have to accurately account for not only DRC (design-rule checking), but also lithography. “We've been developing this router for the last two years and working closely with our customers’ lithography groups to understand the issues they see with the layouts passed to them,” says Krishnamoorthy. He notes that, whereas most DFM (design-for-manufacturing) start-ups focus on analysis or finding DFM problems, more tools are necessary to help fix the problems or to correctly implement designs in the first place. “Finding the problem is probably a quarter of the solution,” says Krishnamoorthy. “At 65 and 45 nm, the number of manufacturing faults is going to be so great, you need to move into the implementation phase, so that you are producing designs that are correct by construction rather than reacting to something that is broken.”
The new router is a hybrid technology that uses engines with and without grids. Krishnamoorthy says the tool stays on the grid for most routes but directs traces off the grid to make connections to vias, for example, to avoid creating unnecessary notches that can degrade performance or cause failures in lithography. Whereas most routers target line and spacing rules, the Sierra router focuses on geometric patterns and automatically flags and fixes routing situations that are lithographically incorrect. These situations include pinching, bridging, overlap, and minimum-space and -width violations. The tool also has a DRC engine to ensure that the targeted process rules are guiding the routing, as well. The DRC engine isn’t of sign-off quality, so you still need a third-party DRC/LVS (layout-versus-schematic) tool for final verification.
Users feed the Sierra Olympus-SOC system a synthesized netlist and variability scenarios describing modes, corners, on-chip variation, metal variation, and lithography rules. The tool then works with third-party critical-area-analysis, simulation, and timing tools to route the design.
