Applied to Extend Litho with Advanced Patterning Film
Staff Reporter -- EDN, July 10, 2006
To meet customers’ critical need for greater optical transparency to deliver precise lithographic alignment in thicker hardmask layers, Santa Clara, Calif.-based capital equipment giant Applied Materials Inc. is unveiling today at the Semicon West tradeshow its Applied Producer advanced patterning film-enhanced (APF-e) system.
The tool was designed to deposit advanced patterning films in sub-70nm Flash and DRAM memory devices and sub-45nm logic applications and is a key enhancement to Applied’s first-generation APF film, the company said.
The APF-e film’s cost-effective hardmask technology allows high selectivity to polysilicon and oxide to enable the key etch patterning steps required for continued geometric scaling.
“Today’s tough patterning challenges require innovative pattern transfer solutions that maximize the lithography process window and improve overall fab economics, especially in high-density chips like flash and DRAM,” said Farhad Moghadam, senior VP and general manager of Applied’s thin films product business group, in a statement.
Applied believes its first-generation APF film is one of the industry’s most successful chemical vapor deposition (CVD) applications and has had a major impact on customers’ ability to move to 90nm and below dimensions. “The new APF-e film enables customers to cost-effectively pattern nano-scale features without additional integration complexity, while reducing their reliance on next-generation lithography solutions,” Moghadam added.
APF-e film is also highly selective to polysilicon (6:1) and oxide etching (15:1) and aims to eliminate the line edge roughness associated with photoresist-only schemes to allow tighter critical dimensional control for improved device performance and yield. APF-e technology also eliminates the expensive wet cleaning steps needed by multi-layer resist processes, the company said.
The APF optically engineered patterning film stack combines the CVD-based amorphous carbon APF or APF-e hardmask films with Applied’s dielectric anti-reflective coating (DARC) films to enable advanced lithography and etching using standard lithography tools. Applied’s APF films are already being used in up to seven layers in 70nm flash memory chips, including shallow trench isolation and sub-40nm gate definition, plus other key applications. Even more layers are expected to be implemented in next-generation devices.
Applied also announced today its Endura integrated liner/barrier (iLB II) system, which it says combines advances in physical vapor deposition (PVD) titanium (Ti) and preclean technologies to reduce resistance in critical contact structures by up to 40 percent.
The system’s PVD enhanced self-ionized plasma (eSIP) chamber deposits a Ti layer on the wafer, plus 30 percent greater bottom coverage over that of the previous system, according to Applied.
Also key is its Siconi Preclean chamber, an improved surface preparation technology for yield-critical transistor and contact interfaces that provides precise removal of oxide from the contact bottom with minimal silicon loss.
“The contact structure is a key, speed-critical electrical component in sub-65nm designs and was becoming the next bottleneck in chip performance,” Moghadam continued. “The new iLB II system extends this differentiated technology to meet the shrinking liner/barrier thickness requirements for contacts used in the 45nm technology node and beyond.”
The 300mm Applied Endura iLB II system provides an integrated combination of preclean, PVD Ti, and CVD TiN for depositing nano-scale films. In addition to enhanced bottom coverage and process symmetry, the eSIP Ti chamber allows improved chamber matching and process repeatability. The system’s Siconi Preclean, already proven for silicide transistor applications, provides a highly selective, soft, chemical clean process that removes oxide without loss of the thin gate nickel-silicide (NiSi) film. In addition, the CVD TiN barrier layer has been enhanced by using a low-temperature process to improve step coverage while delivering higher throughput, the company explained.
Finally, Applied announced a significant enhancement to its Applied Endura copper barrier/seed (CuBS) system with a new Aktiv Preclean chamber, meant to extend the system’s use in 45nm-generation copper-low k interconnects.
In addition to removing polymeric residues and copper oxide from the interconnect, the Aktiv Preclean chamber contains what the company says is the first preclean technology that effectively preserves the integrity of ultra-low k dielectrics, resulting in up to 10 percent improvement in RC delay over previous reactive preclean technologies.
The Aktiv Preclean chamber provides a benign clean process before depositing the barrier and Cu seed layer in copper interconnects. Its highly reactive hydrogen radicals gently clean complex interconnect stacks, assuring low via and line resistance and increasing parametric yield.
The design of the Aktiv Preclean chamber reduces defects and enables up to 30,000 wafers between maintenance cycles, an increase of up to three times over reactive preclean chambers, the company concluded.
