FROM EDN EUROPE: Web-access code checker speeds JTAG test development
By Graham Prophet, EDN Europe -- EDN, April 13, 2006
Asset InterTech, working with Agilent, has extended its online facility for evaluation of BSDL files. Boundary Scan Description Language is the means by which test engineers specify boundary-scan tests or programming operations, compiling a model of the unit under test to apply test patterns or programming algorithms. Asset previously offered an e-mail service for checking users' BSDL files—now it has automated the service and placed it online. When you submit a file, the tools first syntax-check it for correct coding, then analyse the file for semantic errors. An automatic test-pattern generator then creates a set of test vectors in truth-table format, providing a means of verifying that a chip meets the needs of IEEE 1149.1 (boundary scan) and that the BSDL file in turn properly describes the silicon.
The revision in its free service comes as Asset introduces DFT Analyser, a $10,000 tool that, according to a spokesman for Asset, "will drive good JTAG design-for-test practices deeper into the design process." The Analyser queries designers to check that DFT guidelines have been followed, employs a design-verification tool to confirm that they haven't violated any rules, then carries out test-coverage analysis, identifies redundant test points that can be eliminated and outputs a JTAG description of the design for test development. By supporting good practices in DFT earlier in the design process, the outcome is that users will reduce the time necessary to complete their product-test routines.
