The DV appliance
The key to unleashing the power of hardware-assisted verification for the broad market.
By Richard Curtin, Tharas Systems -- EDN, May 12, 2005
With the average system-on-chip design now exceeding 5 million gates, the extension of current (mainly software-based) design verification (DV) methodologies is reaching a dead end. Older tools and methodologies are now working beyond their capabilities and failing to keep pace. To see the inevitable and growing gap, one need only compare the annual increase in performance from software simulators, which is about 10 to 20%, with the exponential increase in chip complexity dictated by Moore 's Law.
In addition, today's designs are growing vastly more complex, with embedded processors and memories, multiple clocks, and tens to hundreds of internal function blocks, which range in complexity from simple "glue" to complete microprocessors.
Hardware-assisted approaches to verification—acceleration and emulation—have long held the promise of attacking the size and complexity challenges, but have typically found use only among a narrow segment of high-end users. Most users would agree the approaches, when successfully implemented, are lifesavers. But concerns about cost, ease-of-use, methodology disruption, scalability—basically, general utility—have kept the majority of IC designers from embracing these tools.
From a practical viewpoint, most potential users of hardware-assisted verification envision large dedicated rooms filled with budget-busting, awkward-sized, and hard-to-maintain equipment that requires as much time compiling, debugging, and re-working the design as the amount of time the tools purport to cut off the verification process.
What the industry needs to drive more mainstream adoption is appliance-like devices that take a page from consumer-market strategies. These devices should be accessible, easy to use, and affordable. Consider the evolution of home-video recorders from expensive, hard-to-use, multiformat VCRs to the ease and functionality offered by today’s TiVo-style devices. No one would argue that design verification is a consumer market, but many of the same principles apply. The appliance approach offers an alternative to the status quo, which involves limited software approaches combined with clunky, expensive hardware options. A "DV appliance" can be a viable means towards achieving broad end-user verification productivity gains.
The problems associated with higher design complexity and gate counts are related to the geometric increase in verification as a function of the push to 90- and 65-nm design starts. According to a 2003 study by Collett International Research, 70% of all designs fail at first silicon, and 67 percent of all those failures are logical and functional failures.
To ameliorate the verification problems, users have added more CPUs and simulation licenses, or have added newer software technologies, such as assertions and formal analysis. Static formal tools impose very steep learning curves while offering relatively limited capacity, often not even as large as some of the medium-sized blocks. The dynamic use of assertions offers a large increase in thoroughness and automation, but at the cost of reduced simulator performance.
Fortunately, today's hardware assisted verification products—both accelerators and emulators—offer orders-of-magnitude increases in validation speeds. However, these products have not achieved broad market adoption because they do not have the characteristics of appliances.
In order for hardware-based approaches to gain a broader foothold they must:
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Be non-disruptive and complementary to existing methodologies
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Provide intuitive debug and analysis capabilities
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Demonstrate tangible ROI for the overall design cycle (not just increases in performance at isolated steps)
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Be generally affordable in the context of design-automation budgets
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Offer more than just gate-level speed ups (address true system-level design needs)
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Be packaged as scalable and flexible systems.
The technological foundation of these appliances will be a key factor in driving broad end-user adoption. As seen by users of today's FPGA (field programmable gate array)-based tools, utilization is limited to the very late stages of RTL verification, due to the tremendous headaches and unpredictability associated with re-spinning the FPGA image. Therefore, the superior alternative for a successful DV appliance architectural foundation is based on custom processors, delivering the speedy compile times, rapid design change turnaround times, extensive debug features and the ability to predictably handle varying device complexities from a few million gates to well over 100 million gates.
These next-generation DV appliances will deliver the same benefits as other broadly successful EDA tools, including ease-of-use, scalable performance, and capacity with clearly understood return-on-investment characteristics. Widespread use of DV appliances can go a long way toward closing the verification gap, while at the same time creating application-level pre-silicon validation methods to ensure first-pass success.
Richard Curtin is the senior vice president of marketing and business development for Tharas Systems in Santa Clara, CA.
